| From 6f4749f01e68aac30145f473933a8c17ea072dc1 Mon Sep 17 00:00:00 2001 |
| From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> |
| Date: Mon, 16 May 2016 11:28:15 +0900 |
| Subject: [PATCH 054/299] drm: rcar-du: Fix H/V sync signal polarity |
| configuration |
| |
| The VSL and HSL bits in the DSMR register set the corresponding |
| horizontal and vertical sync signal polarity to active high. The code |
| got it the wrong way around, fix it. |
| |
| Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit fd1adef3bff0663c5ac31b45bc4a05fafd43d19b) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c |
| +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c |
| @@ -149,8 +149,8 @@ static void rcar_du_crtc_set_display_tim |
| rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0); |
| |
| /* Signal polarities */ |
| - value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL) |
| - | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL) |
| + value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) |
| + | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0) |
| | DSMR_DIPM_DISP | DSMR_CSPM; |
| rcar_du_crtc_write(rcrtc, DSMR, value); |
| |
