| From 768259cf227690716d59217c9237b3b788212d86 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 6 Mar 2017 17:40:43 +0100 |
| Subject: [PATCH 062/286] ARM: dts: r8a7794: Remove unit-address and reg from |
| integrated cache |
| |
| The Cortex-A7 cache controller is an integrated controller, and thus the |
| device node representing it should not have a unit-addresses or reg |
| property. |
| |
| Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=1 dtc warnings") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7794.dtsi | 3 +-- |
| 1 file changed, 1 insertion(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7794.dtsi |
| +++ b/arch/arm/boot/dts/r8a7794.dtsi |
| @@ -56,9 +56,8 @@ |
| next-level-cache = <&L2_CA7>; |
| }; |
| |
| - L2_CA7: cache-controller@0 { |
| + L2_CA7: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| power-domains = <&sysc R8A7794_PD_CA7_SCU>; |
| cache-unified; |
| cache-level = <2>; |
