| From d746cd33f0ee9f81e87e4b0854c118e3b95a3ee6 Mon Sep 17 00:00:00 2001 |
| From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| Date: Sat, 22 Oct 2016 19:05:53 +0300 |
| Subject: [PATCH 052/299] drm: rcar-du: Fix dot clock routing configuration |
| |
| Dot clock routing is setup through different registers depending on the |
| DU generation. The code has been designed for Gen2 and hasn't been |
| updated since. This works thanks to good reset default value, but isn't |
| very safe. Fix it. |
| |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit a3c477b33d6cf015fed50fe5ee23f57e2d579ef4) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/gpu/drm/rcar-du/rcar_du_group.c | 22 +++++++++++++--------- |
| 1 file changed, 13 insertions(+), 9 deletions(-) |
| |
| --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c |
| +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c |
| @@ -105,16 +105,20 @@ static void rcar_du_group_setup(struct r |
| if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) { |
| rcar_du_group_setup_defr8(rgrp); |
| |
| - /* Configure input dot clock routing. We currently hardcode the |
| - * configuration to routing DOTCLKINn to DUn. |
| + /* |
| + * Configure input dot clock routing. We currently hardcode the |
| + * configuration to routing DOTCLKINn to DUn. Register fields |
| + * depend on the DU generation, but the resulting value is 0 in |
| + * all cases. |
| + * |
| + * On Gen2 a single register in the first group controls dot |
| + * clock selection for all channels, while on Gen3 dot clocks |
| + * are setup through per-group registers, only available when |
| + * the group has two channels. |
| */ |
| - rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE | |
| - DIDSR_LCDS_DCLKIN(2) | |
| - DIDSR_LCDS_DCLKIN(1) | |
| - DIDSR_LCDS_DCLKIN(0) | |
| - DIDSR_PDCS_CLK(2, 0) | |
| - DIDSR_PDCS_CLK(1, 0) | |
| - DIDSR_PDCS_CLK(0, 0)); |
| + if ((rcdu->info->gen < 3 && rgrp->index == 0) || |
| + (rcdu->info->gen == 3 && rgrp->num_crtcs > 1)) |
| + rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE); |
| } |
| |
| if (rcdu->info->gen >= 3) |
