| From 6a9b216413c5b1c2f285637f971c45a04f281fcc Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 6 Mar 2017 17:40:37 +0100 |
| Subject: [PATCH 056/286] ARM: dts: r8a7743: Remove unit-address and reg from |
| integrated cache |
| |
| The Cortex-A15 cache controller is an integrated controller, and thus |
| the device node representing it should not have a unit-addresses or reg |
| property. |
| |
| Fixes: 34e8d993a68ae459 ("ARM: dts: r8a7743: initial SoC device tree") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 37f0c804e57ac93ca37a98aa5a210c6b73e6572a) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7743.dtsi | 3 +-- |
| 1 file changed, 1 insertion(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7743.dtsi |
| +++ b/arch/arm/boot/dts/r8a7743.dtsi |
| @@ -32,9 +32,8 @@ |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| - L2_CA15: cache-controller@0 { |
| + L2_CA15: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| cache-unified; |
| cache-level = <2>; |
| power-domains = <&sysc R8A7743_PD_CA15_SCU>; |
