| From 101cfba35e6e943945a2c54925cea00f50882286 Mon Sep 17 00:00:00 2001 |
| From: Simon Horman <horms+renesas@verge.net.au> |
| Date: Tue, 13 Sep 2016 12:57:02 +0200 |
| Subject: [PATCH 210/299] ARM: dts: koelsch: enable UHS for SDHI 0, 1 & 3 |
| |
| Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}. |
| |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> |
| (cherry picked from commit d3cec922fe2030235588aa6fe53d6470b4e7496f) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7791-koelsch.dts | 33 ++++++++++++++++++++++++++++++--- |
| 1 file changed, 30 insertions(+), 3 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7791-koelsch.dts |
| +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts |
| @@ -360,16 +360,37 @@ |
| sdhi0_pins: sd0 { |
| groups = "sdhi0_data4", "sdhi0_ctrl"; |
| function = "sdhi0"; |
| + power-source = <3300>; |
| + }; |
| + |
| + sdhi0_pins_uhs: sd0_uhs { |
| + groups = "sdhi0_data4", "sdhi0_ctrl"; |
| + function = "sdhi0"; |
| + power-source = <1800>; |
| }; |
| |
| sdhi1_pins: sd1 { |
| groups = "sdhi1_data4", "sdhi1_ctrl"; |
| function = "sdhi1"; |
| + power-source = <3300>; |
| + }; |
| + |
| + sdhi1_pins_uhs: sd1_uhs { |
| + groups = "sdhi1_data4", "sdhi1_ctrl"; |
| + function = "sdhi1"; |
| + power-source = <1800>; |
| }; |
| |
| sdhi2_pins: sd2 { |
| groups = "sdhi2_data4", "sdhi2_ctrl"; |
| function = "sdhi2"; |
| + power-source = <3300>; |
| + }; |
| + |
| + sdhi2_pins_uhs: sd2_uhs { |
| + groups = "sdhi2_data4", "sdhi2_ctrl"; |
| + function = "sdhi2"; |
| + power-source = <1800>; |
| }; |
| |
| qspi_pins: qspi { |
| @@ -454,33 +475,39 @@ |
| |
| &sdhi0 { |
| pinctrl-0 = <&sdhi0_pins>; |
| - pinctrl-names = "default"; |
| + pinctrl-1 = <&sdhi0_pins_uhs>; |
| + pinctrl-names = "default", "state_uhs"; |
| |
| vmmc-supply = <&vcc_sdhi0>; |
| vqmmc-supply = <&vccq_sdhi0>; |
| cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; |
| + sd-uhs-sdr50; |
| status = "okay"; |
| }; |
| |
| &sdhi1 { |
| pinctrl-0 = <&sdhi1_pins>; |
| - pinctrl-names = "default"; |
| + pinctrl-1 = <&sdhi1_pins_uhs>; |
| + pinctrl-names = "default", "state_uhs"; |
| |
| vmmc-supply = <&vcc_sdhi1>; |
| vqmmc-supply = <&vccq_sdhi1>; |
| cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; |
| + sd-uhs-sdr50; |
| status = "okay"; |
| }; |
| |
| &sdhi2 { |
| pinctrl-0 = <&sdhi2_pins>; |
| - pinctrl-names = "default"; |
| + pinctrl-1 = <&sdhi2_pins_uhs>; |
| + pinctrl-names = "default", "state_uhs"; |
| |
| vmmc-supply = <&vcc_sdhi2>; |
| vqmmc-supply = <&vccq_sdhi2>; |
| cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; |
| + sd-uhs-sdr50; |
| status = "okay"; |
| }; |
| |