From 94068d8c8be80b81e019683b4997a46627e3dd86 Mon Sep 17 00:00:00 2001
From: Alan Tull <atull@opensource.altera.com>
Date: Tue, 12 Jul 2016 14:07:08 -0500
Subject: [PATCH 057/103] ARM: socfpga: add bindings doc for arria10 fpga
 manager

Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-By: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt |   19 ++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt

--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Altera SOCFPGA Arria10 FPGA Manager
+
+Required properties:
+- compatible : should contain "altr,socfpga-a10-fpga-mgr"
+- reg        : base address and size for memory mapped io.
+               - The first index is for FPGA manager register access.
+               - The second index is for writing FPGA configuration data.
+- resets     : Phandle and reset specifier for the device's reset.
+- clocks     : Clocks used by the device.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ffd03000 {
+		compatible = "altr,socfpga-a10-fpga-mgr";
+		reg = <0xffd03000 0x100
+		       0xffcfe400 0x20>;
+		clocks = <&l4_mp_clk>;
+		resets = <&rst FPGAMGR_RESET>;
+	};