| From dbc9e4f4f5fa52118578558cbfff17229103a2ed Mon Sep 17 00:00:00 2001 |
| From: Dinh Nguyen <dinguyen@opensource.altera.com> |
| Date: Wed, 20 Nov 2013 09:39:17 -0600 |
| Subject: [PATCH 26/39] ARM: socfpga: dts: Correct the parent clock for |
| l3_sp_clk and dbg_clk |
| |
| The l3_sp_clk's parent should be the l3_mp_clk. This will account for |
| the extra divider that is present for the l3_mp_clk. |
| |
| The dbg_clk's parent should be the dbg_at_clk. This will account for |
| the extra divider that is present for the dbg_at_clk. |
| |
| Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> |
| (cherry picked from commit c5dab6e2c1f7bbf33ec855cebae92a1566ed6d04) |
| Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> |
| --- |
| arch/arm/boot/dts/socfpga.dtsi | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi |
| index 1e3c833dfbd2..7860935ae3a2 100644 |
| --- a/arch/arm/boot/dts/socfpga.dtsi |
| +++ b/arch/arm/boot/dts/socfpga.dtsi |
| @@ -318,7 +318,7 @@ |
| l3_sp_clk: l3_sp_clk { |
| #clock-cells = <0>; |
| compatible = "altr,socfpga-gate-clk"; |
| - clocks = <&mainclk>; |
| + clocks = <&l3_mp_clk>; |
| div-reg = <0x64 2 2>; |
| }; |
| |
| @@ -349,7 +349,7 @@ |
| dbg_clk: dbg_clk { |
| #clock-cells = <0>; |
| compatible = "altr,socfpga-gate-clk"; |
| - clocks = <&dbg_base_clk>; |
| + clocks = <&dbg_at_clk>; |
| div-reg = <0x68 2 2>; |
| clk-gate = <0x60 5>; |
| }; |
| -- |
| 2.6.2 |
| |
