| From 3c54e187d03e0a96df8e7c4abff76d1a4d7ea9f7 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Thu, 29 Mar 2018 11:02:18 +0200 |
| Subject: [PATCH 1601/1795] clk: renesas: r8a7791/r8a7793: Fix LB clock divider |
| |
| The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where |
| the LB clock divider depends on the value of the MD18 pin. |
| |
| On R-Car M2-W and M2-N, the LB clock divider is fixed to 24. Hence |
| model the clock as a fixed factor clock instead. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Reviewed-by: Simon Horman <horms+renesas@verge.net.au> |
| Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| (cherry picked from commit 6041ce57f2c8c231017a1b4f7a71b606bb1c1016) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c |
| index 820b220b09cc..1b91f03b7598 100644 |
| --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c |
| @@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = { |
| |
| /* Core Clock Outputs */ |
| DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), |
| - DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), |
| DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), |
| DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), |
| DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), |
| @@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = { |
| DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1), |
| DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1), |
| DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1), |
| + DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1), |
| DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1), |
| DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1), |
| DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1), |
| -- |
| 2.19.0 |
| |