)]}'
{
  "id": "f515ae4673d42c673faf1b0746c9c82ddab465e9",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "6ae892ea75e24042edb182688953e0fae307ea63",
      "name": "0001-ARM-Add-msi.h-to-Kbuild.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "53b07a149c714bc40ee856934827fcf9a87e959a",
      "name": "0001-ARM-socfpga-dts-add-cpu1-start-addr-for-Arria-10.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6e6c3d94c317009635870a26c63f06d494159cde",
      "name": "0001-nios2-Export-get_cycles.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "08b4c2fcd955ca7d0fa2259946c25c1fa6f0c78a",
      "name": "0001-usage-documentation-for-FPGA-manager-core.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c48258e83cd6ec6aa2798bbad7c0b88011ce1ff1",
      "name": "0002-ARM-socfpga-dts-disable-the-sdmmc-and-uart-nodes-in-.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "a6f9036e0873d98c799f94e7080dfce048a6e86f",
      "name": "0002-PCI-altera-Add-Altera-PCIe-host-controller-driver.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "82137d40ba74aeebf87589bec83624688e7962c5",
      "name": "0002-fpga-manager-add-sysfs-interface-document.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "047757cd990a71b1016845613e8e988e47d1e515",
      "name": "0002-nios2-check-number-of-timer-instances.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7c20a5f3d9b824cd9c4937ec1d6de4e4da8dbfef",
      "name": "0003-ARM-socfpga-dts-enable-UART1-for-the-debug-uart.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "5aa5193892080de441b1a3f7f15ca163e3bffe87",
      "name": "0003-PCI-altera-Add-Altera-PCIe-MSI-driver.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "de36673b7b13e8f8c598bac05dce2d35fc095385",
      "name": "0003-add-FPGA-manager-core.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "675af3d75546ecd5c5810fdbae1f79c7bcb036bb",
      "name": "0003-nios2-time-Migrate-to-new-set-state-interface.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "1b29cfd65998836df10bc5b1526d15af19b84bae",
      "name": "0004-ARM-socfpga-dts-rename-socdk-board-file-to-socdk_sdm.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "5c9de4ddf4ca0ca1270cda4057ed17bed0d83120",
      "name": "0004-PCI-altera-Fix-loop-in-tlp_read_packet.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "167c56dde4a1b10bde574db3e2c30972f02a1a13",
      "name": "0004-fpga-manager-add-driver-for-socfpga-fpga-manager.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "baa96df37877dc0da9a8dbe316633a07c62870f6",
      "name": "0004-nios2-fixed-variable-imm16-to-s16.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "da9d097b616a2b85fea35e83ed1be29ce7a9aa28",
      "name": "0005-ARM-socfpga-dts-Add-a-clock-node-for-sdmmc-CIU.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "e2155bd7201f4fef3c0e4e7543acee4bb5903006",
      "name": "0005-MAINTAINERS-add-fpga-manager-framework.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "eb5b73aec62f92922960e6f3e42b7aed2465b2fc",
      "name": "0005-PCI-altera-Fix-Requester-ID-for-config-accesses.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6a957025026107ce35bbd4817b420ae4af9afc85",
      "name": "0005-nios2-remove-unused-statistic-counters.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "bb8464af9922f34fdf7c9a82a4e0a6a20151466a",
      "name": "0006-ARM-socfpga-dts-Add-multicast-bins-and-unicast-filte.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "088df8c3ed3aa4e054c1292a76483ae1bb57601a",
      "name": "0006-ARM-socfpga_defconfig-enable-fpga-manager.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "1aa865af88d28c3ebde76c7da8df1ddd302ff494",
      "name": "0006-PCI-altera-Check-TLP-completion-status.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "358f2d78856dbbecb0c675d8163b15520e39b9f2",
      "name": "0006-nios2-Add-Max10-device-tree.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7c47e45d3ba27480ceafb7a0f67377256de24556",
      "name": "0007-ARM-socfpga-dts-Add-tx-fifo-depth-and-rx-fifo-depth-.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "9cdde6b26b40055cb181124b79858b446d33f2aa",
      "name": "0007-ARM-socfpga-dts-add-fpga-manager.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "31edf50434ef1b9b78a7d13b97a04009c8bcda75",
      "name": "0007-PCI-altera-Fix-error-when-INTx-is-4.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "d8e96180ed37792ddf99e41cbf3ed4ca66dcf7c0",
      "name": "0007-nios2-add-Max10-defconfig.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "58ecf78354bb52ef634077ab5ed8f5ab17004915",
      "name": "0008-ARM-socfpga-dts-add-clocks-to-the-Arria10-platform.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2d86f8f993cd48162ab9600ec3530d3799edee09",
      "name": "0008-nios2-Fix-unused-variable-warning.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "733fb745b94545c7fb97724264cee7ebca264347",
      "name": "0009-ARM-socfpga-Add-support-for-UART1-debug-uart-for-ear.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "109ba8570d775837c2151d876285fddfbfe9a87e",
      "name": "0009-nios2-Switch-to-generic-__xchg.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "5c3af2eecb7003672f597d668b9d5b4fe1ad0ea4",
      "name": "0010-ARM-socfpga-remove-the-need-to-map-uart_io_desc.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2b3e2290fdf6ea93dfa55106202df74410492385",
      "name": "0011-ARM-socfpga-dts-add-the-a9-scu-node.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f23ab91db1fa2b093a031b391696821974ff062f",
      "name": "0012-ARM-socfpga-use-of_iomap-to-map-the-SCU.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "e4337db46f111d4cd08f0e1464a6b6219d427e6a",
      "name": "0013-clk-socfpga-update-clk.h-so-for-Arria10-platform-to-.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "ecafd3c91993d0023e09d5da610d13ea7153a211",
      "name": "0014-clk-socfpga-add-a-clock-driver-for-the-Arria-10-plat.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4e4ff2c381bbf9fc5c4e978556697aef09ad3556",
      "name": "0015-ARM-socfpga-dts-add-the-a9-scu-node-for-arria10.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c12f1e4f34720cce9aae5589974bff5d7115198f",
      "name": "0016-ARM-socfpga-dts-add-enable-method-property-for-cpu-n.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c635a754a2f4bd7ded68c881631bb1503cad9500",
      "name": "0017-clk-of-helper-for-filling-parent-clock-array-and-ret.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "d60f03010d7a98e931011ca6fca78bae7f08b520",
      "name": "0018-clk-socfpga-make-use-of-of_clk_parent_fill-helper-fu.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "290e3bfd5f5f65a1b2be025dc4cf990575c2cb76",
      "name": "0019-ARM-socfpga-use-CPU_METHOD_OF_DECLARE-for-socfpga_cy.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "03e89bdbf7ba8b8572d857d6d138dfa64fa0578e",
      "name": "0020-ARM-socfpga-add-CPU_METHOD_OF_DECLARE-for-Arria-10.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "cc2023bd3f835a4eca756bbcc0e2ad00625075b2",
      "name": "0021-ARM-socfpga-dts-enable-ethernet-for-Arria10-devkit.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "509f3d165b377fc5a512f6e1b2d40cb7899a898d",
      "name": "0022-ARM-socfpga-support-suspend-to-ram.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "9f887cab4b7618ca9aacd9f56611f68535701fe6",
      "name": "0023-ARM-dts-socfpga-enable-the-data-and-instruction-pref.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "b14235a2d3db39b4bbf47565074c83cc5ecba518",
      "name": "0024-ARM-dts-socfpga-use-stdout-path-for-chosen-node.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "de8496c282d6596af597be0d4c7b7dff697685a7",
      "name": "0025-ARM-socfpga-add-reset-for-the-Arria-10-platform.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "5535063cdd53c11bc618eea8293bb5b9a6308ba1",
      "name": "0026-ARM-socfpga-dts-Correct-the-parent-clock-for-l3_sp_c.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "325f8b6ace2d1ff63312a24ef7fd12891378a4e2",
      "name": "0027-ARM-socfpga-dts-Fix-gpio-dts-entry-for-the-correct-c.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7c31785f8350c202886e1cf8dba8c3f7f68663b0",
      "name": "0028-ARM-socfpga-dts-add-osc1-as-a-possible-parent-for-db.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "e58c714facde5b1c580a55e676bc1fbd31495d15",
      "name": "0029-reset-socfpga-Update-reset-socfpga-to-read-the-altr-.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "bf8af3eea98eb0650befa6c78c41a1f5cf59f7bb",
      "name": "0030-dt-bindings-Add-reset-manager-offsets-for-Arria10.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "0b3a9427c2eddb459cb40104249473ccfb250f59",
      "name": "0031-ARM-socfpga-dts-add-altr-modrst-offset-property.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "a974fe4300527ff4b2c5b8fbac4f5121ee216293",
      "name": "0032-ARM-socfpga-dts-Add-resets-for-EMACs-on-Arria10.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "6c05e33ba537d61c18a323510c7a128f42d2601b",
      "name": "0033-clk-socfpga-Add-a-second-parent-option-for-the-dbg_b.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4fb3aa784a43d657cee00746b665dc468f97ca62",
      "name": "0034-EDAC-altera-Generalize-driver-to-use-DT-Memory-size.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c17a3f2370274302a3e8e296b13fae6c658716bd",
      "name": "0035-EDAC-altera-Refactor-for-Altera-CycloneV-SoC.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "8b909cbafe40f16e1f438428eabe4a11bdd67616",
      "name": "0036-EDAC-altera-Add-Arria10-EDAC-support.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c19640cb422b332455f42e0f4e622affdb71450a",
      "name": "0037-arm-socfpga-dts-Add-Arria10-SDRAM-EDAC-DTS-support.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "e7cd3c5499eae202d652ac5c3af684794903d0ad",
      "name": "0038-EDAC-altera-Do-not-allow-suspend-when-EDAC-is-enable.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "3359223d5f635ca6e729a967aca63712ad115f68",
      "name": "0039-ARM-dts-socfpga-Add-support-of-Terasic-DE0-Atlas-boa.patch"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "513e6a407a4015a62f52c5d43618e24e3df0ae3b",
      "name": "arm-socfpga-fix-build-error-due-to-secondary_startup.patch"
    }
  ]
}
