| From ae7a1af011c2dc22c6c9d3238a6a9d2445a6d348 Mon Sep 17 00:00:00 2001 |
| From: Chris Paterson <chris.paterson2@renesas.com> |
| Date: Tue, 22 Nov 2016 13:46:01 +0000 |
| Subject: [PATCH 010/255] clk: renesas: r8a7796: Add CANFD clock |
| |
| Based on a patch for r8a7795 by Ramesh Shanmugasundaram. |
| |
| Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 9e620beecdf40303c950f344806730093e5d08ae) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| @@ -103,6 +103,7 @@ static const struct cpg_core_clk r8a7796 |
| DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
| DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
| |
| + DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
| DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
| |
| DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
