| From fb85a83e56bbe1a3899b8293a2db442696aa7631 Mon Sep 17 00:00:00 2001 |
| From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
| Date: Mon, 21 Nov 2016 22:26:45 +0000 |
| Subject: [PATCH 039/103] fpga zynq: Fix incorrect ISR state on bootup |
| |
| It is best practice to clear and mask all interrupts before |
| associating the IRQ, and this should be done after the clock |
| is enabled. |
| |
| This corrects a bad result from zynq_fpga_ops_state on bootup |
| where left over latched values in INT_STS_OFFSET caused it to |
| report an unconfigured FPGA as configured. |
| |
| After this change the boot up operating state for an unconfigured |
| FPGA reports 'unknown'. |
| |
| Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
| Acked-by: Alan Tull <atull@opensource.altera.com> |
| Acked-by: Moritz Fischer <moritz.fischer@ettus.com> |
| --- |
| drivers/fpga/zynq-fpga.c | 17 ++++++++++------- |
| 1 file changed, 10 insertions(+), 7 deletions(-) |
| |
| --- a/drivers/fpga/zynq-fpga.c |
| +++ b/drivers/fpga/zynq-fpga.c |
| @@ -437,13 +437,6 @@ static int zynq_fpga_probe(struct platfo |
| return priv->irq; |
| } |
| |
| - err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, |
| - dev_name(dev), priv); |
| - if (err) { |
| - dev_err(dev, "unable to request IRQ\n"); |
| - return err; |
| - } |
| - |
| priv->clk = devm_clk_get(dev, "ref_clk"); |
| if (IS_ERR(priv->clk)) { |
| dev_err(dev, "input clock not found\n"); |
| @@ -459,6 +452,16 @@ static int zynq_fpga_probe(struct platfo |
| /* unlock the device */ |
| zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); |
| |
| + zynq_fpga_write(priv, INT_MASK_OFFSET, 0xFFFFFFFF); |
| + zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); |
| + err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev), |
| + priv); |
| + if (err) { |
| + dev_err(dev, "unable to request IRQ\n"); |
| + clk_disable_unprepare(priv->clk); |
| + return err; |
| + } |
| + |
| clk_disable(priv->clk); |
| |
| err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", |
