| From b8e93abe1d9a7e71c40997d861fa216ff96a0082 Mon Sep 17 00:00:00 2001 |
| From: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Date: Fri, 12 Apr 2013 17:57:58 -0300 |
| Subject: drm/i915: print Gen5+ CPU/PCH poison interrupts |
| |
| This is bad news and shouldn't be happening. |
| |
| V2: Rebase. |
| |
| Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Reviewed-by: Imre Deak <imre.deak@intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit de032bf40a52dbbada11e071d150d2c062b5527e) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_irq.c | 13 +++++++++++-- |
| drivers/gpu/drm/i915/i915_reg.h | 2 ++ |
| 2 files changed, 13 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_irq.c |
| +++ b/drivers/gpu/drm/i915/i915_irq.c |
| @@ -1014,6 +1014,9 @@ static void ivb_err_int_handler(struct d |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 err_int = I915_READ(GEN7_ERR_INT); |
| |
| + if (err_int & ERR_INT_POISON) |
| + DRM_ERROR("Poison interrupt\n"); |
| + |
| if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
| if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| @@ -1034,6 +1037,9 @@ static void cpt_serr_int_handler(struct |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 serr_int = I915_READ(SERR_INT); |
| |
| + if (serr_int & SERR_INT_POISON) |
| + DRM_ERROR("PCH poison interrupt\n"); |
| + |
| if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
| if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| false)) |
| @@ -1252,6 +1258,9 @@ static irqreturn_t ironlake_irq_handler( |
| if (de_iir & DE_PIPEB_VBLANK) |
| drm_handle_vblank(dev, 1); |
| |
| + if (de_iir & DE_POISON) |
| + DRM_ERROR("Poison interrupt\n"); |
| + |
| if (de_iir & DE_PIPEA_FIFO_UNDERRUN) |
| if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| @@ -2533,7 +2542,7 @@ static void ibx_irq_postinstall(struct d |
| |
| if (HAS_PCH_IBX(dev)) { |
| mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | |
| - SDE_TRANSA_FIFO_UNDER; |
| + SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
| } else { |
| mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; |
| |
| @@ -2554,7 +2563,7 @@ static int ironlake_irq_postinstall(stru |
| u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
| DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | |
| - DE_PIPEA_FIFO_UNDERRUN; |
| + DE_PIPEA_FIFO_UNDERRUN | DE_POISON; |
| u32 render_irqs; |
| |
| dev_priv->irq_mask = ~display_mask; |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -639,6 +639,7 @@ |
| |
| #define ERROR_GEN6 0x040a0 |
| #define GEN7_ERR_INT 0x44040 |
| +#define ERR_INT_POISON (1<<31) |
| #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
| #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
| #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
| @@ -3816,6 +3817,7 @@ |
| #define SDEIER 0xc400c |
| |
| #define SERR_INT 0xc4040 |
| +#define SERR_INT_POISON (1<<31) |
| #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
| #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) |
| #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) |
