| From 5ac0a9430796e59ed945dd045d500f9d0c0f8e0f Mon Sep 17 00:00:00 2001 |
| From: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Date: Fri, 19 Apr 2013 11:24:39 +0200 |
| Subject: drm/i915: Fixup non-24bpp support for VGA screens on Haswell |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| The LPT PCH only supports 8bpc, so we need to force the pipe bpp |
| to the right value. |
| |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 2a7aceecf15a463ba6bfa83b6579e75bb4703cd9) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_crt.c | 4 ++++ |
| 1 file changed, 4 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c |
| index 58b4a53715cd..1b9ebf4b77fc 100644 |
| --- a/drivers/gpu/drm/i915/intel_crt.c |
| +++ b/drivers/gpu/drm/i915/intel_crt.c |
| @@ -207,6 +207,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, |
| if (HAS_PCH_SPLIT(dev)) |
| pipe_config->has_pch_encoder = true; |
| |
| + /* LPT FDI RX only supports 8bpc. */ |
| + if (HAS_PCH_LPT(dev)) |
| + pipe_config->pipe_bpp = 24; |
| + |
| return true; |
| } |
| |
| -- |
| 1.8.5.rc3 |
| |
