| From 069a4e64a35dc46ffd6b5b89f1d3ee18ed919ddf Mon Sep 17 00:00:00 2001 |
| From: Jani Nikula <jani.nikula@intel.com> |
| Date: Thu, 25 Apr 2013 16:49:25 +0300 |
| Subject: drm/i915: hsw backlight registers need transcoder instead of pipe |
| |
| v2: Make TRANSCODER_EDP handling more explicit. (Imre) |
| |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Reviewed-by: Imre Deak <imre.deak@intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 35ffda4883a8d3f75632d7389dc96a25640033f0) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 4 ++++ |
| drivers/gpu/drm/i915/intel_panel.c | 7 ++++++- |
| 2 files changed, 10 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -2097,6 +2097,10 @@ |
| #define BLM_PIPE_A (0 << 29) |
| #define BLM_PIPE_B (1 << 29) |
| #define BLM_PIPE_C (2 << 29) /* ivb + */ |
| +#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
| +#define BLM_TRANSCODER_B BLM_PIPE_B |
| +#define BLM_TRANSCODER_C BLM_PIPE_C |
| +#define BLM_TRANSCODER_EDP (3 << 29) |
| #define BLM_PIPE(pipe) ((pipe) << 29) |
| #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
| #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) |
| --- a/drivers/gpu/drm/i915/intel_panel.c |
| +++ b/drivers/gpu/drm/i915/intel_panel.c |
| @@ -344,6 +344,8 @@ void intel_panel_enable_backlight(struct |
| enum pipe pipe) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| + enum transcoder cpu_transcoder = |
| + intel_pipe_to_cpu_transcoder(dev_priv, pipe); |
| unsigned long flags; |
| |
| spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
| @@ -374,7 +376,10 @@ void intel_panel_enable_backlight(struct |
| else |
| tmp &= ~BLM_PIPE_SELECT; |
| |
| - tmp |= BLM_PIPE(pipe); |
| + if (cpu_transcoder == TRANSCODER_EDP) |
| + tmp |= BLM_TRANSCODER_EDP; |
| + else |
| + tmp |= BLM_PIPE(cpu_transcoder); |
| tmp &= ~BLM_PWM_ENABLE; |
| |
| I915_WRITE(reg, tmp); |
