blob: 50370ed120dd070e8d6eaa66e7784392173eedb6 [file] [log] [blame]
From 9b72e6a45a1bd7a34003f4081443639cfd075dac Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat, 20 Apr 2013 17:19:46 +0200
Subject: drm/i915: shovel compute clock into crtc->config.dpll on ilk
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This was somehow lost in the pipe_config->dpll introduction in
commit f47709a9502f3715cc488b788ca91cf0c142b1b1
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu Mar 28 10:42:02 2013 +0100
drm/i915: create pipe_config->dpll for clock state
While at it, extract a few small helpers for common computations.
v2: Use the newly added helpers more thanks to Ville's trick to
typedef the legacy intel_clock_t as the new-world struct dpll.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 7429e9d4bfcfd08a00ed7b760386bd81a60e91d6)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++++++------------
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1afc053c39cc..eefc8e2ebe94 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -549,13 +549,18 @@ static void pineview_clock(int refclk, intel_clock_t *clock)
clock->dot = clock->vco / clock->p;
}
+static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
+{
+ return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
+}
+
static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
if (IS_PINEVIEW(dev)) {
pineview_clock(refclk, clock);
return;
}
- clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
+ clock->m = i9xx_dpll_compute_m(clock);
clock->p = clock->p1 * clock->p2;
clock->vco = refclk * clock->m / (clock->n + 2);
clock->dot = clock->vco / clock->p;
@@ -4247,6 +4252,16 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
crtc->config.clock_set = true;
}
+static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
+{
+ return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
+}
+
+static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
+{
+ return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
+}
+
static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
intel_clock_t *reduced_clock)
{
@@ -4254,18 +4269,15 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = crtc->pipe;
u32 fp, fp2 = 0;
- struct dpll *clock = &crtc->config.dpll;
if (IS_PINEVIEW(dev)) {
- fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
+ fp = pnv_dpll_compute_fp(&crtc->config.dpll);
if (reduced_clock)
- fp2 = (1 << reduced_clock->n) << 16 |
- reduced_clock->m1 << 8 | reduced_clock->m2;
+ fp2 = pnv_dpll_compute_fp(reduced_clock);
} else {
- fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
+ fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
if (reduced_clock)
- fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
- reduced_clock->m2;
+ fp2 = i9xx_dpll_compute_fp(reduced_clock);
}
I915_WRITE(FP0(pipe), fp);
@@ -5604,8 +5616,13 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
}
+static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
+{
+ return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
+}
+
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
- intel_clock_t *clock, u32 *fp,
+ u32 *fp,
intel_clock_t *reduced_clock, u32 *fp2)
{
struct drm_crtc *crtc = &intel_crtc->base;
@@ -5645,7 +5662,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
} else if (is_sdvo && is_tv)
factor = 20;
- if (clock->m < factor * clock->n)
+ if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
*fp |= FP_CB_TUNE;
if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -5669,11 +5686,11 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
dpll |= DPLL_DVO_HIGH_SPEED;
/* compute bitmask from p1 value */
- dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
/* also FPA1 */
- dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+ dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
- switch (clock->p2) {
+ switch (intel_crtc->config.dpll.p2) {
case 5:
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
break;
@@ -5768,12 +5785,11 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
if (intel_crtc->config.has_pch_encoder) {
struct intel_pch_pll *pll;
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
if (has_reduced_clock)
- fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
- reduced_clock.m2;
+ fp2 = i9xx_dpll_compute_fp(&reduced_clock);
- dpll = ironlake_compute_dpll(intel_crtc, &clock,
+ dpll = ironlake_compute_dpll(intel_crtc,
&fp, &reduced_clock,
has_reduced_clock ? &fp2 : NULL);
--
1.8.5.rc3