blob: 8fa445cafbccc1325f0394486b1b28e97b369ea4 [file] [log] [blame]
From 7a4b736b75ae8af323ae98892804544622892b3a Mon Sep 17 00:00:00 2001
From: Daniel Vetter <>
Date: Fri, 19 Apr 2013 11:14:35 +0200
Subject: drm/i915: don't force matching p1 for g4x/ilk+ reduced pll settings
g4x dplls and ilk+ pch plls have a separate field for the reduced p1
setting, so this restriction does not apply. Only older platforms have
the restriction that the p1 divisors must match.
This unnecessary restriction has been introduced in
commit cec2f356d59d9e070413e5966a3c5a1af136d948
Author: Sean Paul <>
Date: Tue Jan 10 15:09:36 2012 -0800
drm/i915: Only look for matching clocks for LVDS downcloc
Note that with lvds the p2 divisors _always_ match for LVDS, and we
don't support auto-downclocking anywhere else. On eDP downclocking
works with separate data m/n settings, using the same link clock.
Cc: Sean Paul <>
Reviewed-by: Sean Paul <>
Signed-off-by: Daniel Vetter <>
(cherry picked from commit 4f4134ace04fd5b0e8734b65f4046e7aa2e39393)
Signed-off-by: Darren Hart <>
drivers/gpu/drm/i915/intel_display.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 07f526ff5557..a22bcf576ea9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -685,9 +685,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
if (!intel_PLL_is_valid(dev, limit,
- if (match_clock &&
- clock.p != match_clock->p)
- continue;
this_err = abs( - target);
if (this_err < err_most) {