blob: ac129d35a0c99b788a36a19d2aa6859ce9771a8f [file] [log] [blame]
From a2e5bc8abb3c38173c900dd9737f8a565c1d5357 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Thu, 25 Apr 2013 12:55:02 -0700
Subject: drm/i915: move PCH pfit controls into pipe_config
And put the pfit stuff into substructs while we're at it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit b074cec8c652f2d273907a4b35239b4766c894ac)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 65 +++++++++++++++++-------------------
drivers/gpu/drm/i915/intel_dp.c | 6 ++--
drivers/gpu/drm/i915/intel_drv.h | 18 +++++++---
drivers/gpu/drm/i915/intel_lvds.c | 6 ++--
drivers/gpu/drm/i915/intel_panel.c | 25 ++++++++------
7 files changed, 63 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index afc6977303c6..a540b1f2354e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1022,8 +1022,6 @@ typedef struct drm_i915_private {
struct sdvo_device_mapping sdvo_mappings[2];
/* indicate whether the LVDS_BORDER should be enabled or not */
unsigned int lvds_border_bits;
- /* Panel fitter placement and size for Ironlake+ */
- u32 pch_pf_pos, pch_pf_size;
struct drm_crtc *plane_to_crtc_mapping[3];
struct drm_crtc *pipe_to_crtc_mapping[3];
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cfaf6bead217..70a1e9ca87d3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -995,7 +995,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
/* Can only use the always-on power well for eDP when
* not using the panel fitter, and when not using motion
* blur mitigation (which we don't support). */
- if (dev_priv->pch_pf_size)
+ if (intel_crtc->config.pch_pfit.size)
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
else
temp |= TRANS_DDI_EDP_INPUT_A_ON;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ab5758374f8d..0af841ebc505 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3225,6 +3225,28 @@ void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
}
}
+static void ironlake_pfit_enable(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = crtc->pipe;
+
+ if (crtc->config.pch_pfit.size &&
+ intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
+ /* Force use of hard-coded filter coefficients
+ * as some pre-programmed values are broken,
+ * e.g. x201.
+ */
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
+ PF_PIPE_SEL_IVB(pipe));
+ else
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
+ I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
+ }
+}
+
static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -3269,21 +3291,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
encoder->pre_enable(encoder);
/* Enable panel fitting for LVDS */
- if (dev_priv->pch_pf_size &&
- (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
- intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
- /* Force use of hard-coded filter coefficients
- * as some pre-programmed values are broken,
- * e.g. x201.
- */
- if (IS_IVYBRIDGE(dev))
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
- PF_PIPE_SEL_IVB(pipe));
- else
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
- I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
- }
+ ironlake_pfit_enable(intel_crtc);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -3353,17 +3361,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_ddi_enable_pipe_clock(intel_crtc);
/* Enable panel fitting for eDP */
- if (dev_priv->pch_pf_size &&
- intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
- /* Force use of hard-coded filter coefficients
- * as some pre-programmed values are broken,
- * e.g. x201.
- */
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
- PF_PIPE_SEL_IVB(pipe));
- I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
- I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
- }
+ ironlake_pfit_enable(intel_crtc);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -3621,11 +3619,11 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
* register description and PRM.
*/
DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
- pipe_config->pfit_control,
- pipe_config->pfit_pgm_ratios);
+ pipe_config->gmch_pfit.control,
+ pipe_config->gmch_pfit.pgm_ratios);
- I915_WRITE(PFIT_PGM_RATIOS, pipe_config->pfit_pgm_ratios);
- I915_WRITE(PFIT_CONTROL, pipe_config->pfit_control);
+ I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
+ I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
}
static void valleyview_crtc_enable(struct drm_crtc *crtc)
@@ -5812,6 +5810,9 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
/* XXX: Should check for edp transcoder here, but thanks to init
* sequence that's not yet available. Just in case desktop eDP
* on PORT D is possible on haswell, too. */
+ /* Even the eDP panel fitter is outside the always-on well. */
+ if (I915_READ(PF_WIN_SZ(crtc->pipe)))
+ enable = true;
}
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
@@ -5821,10 +5822,6 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
enable = true;
}
- /* Even the eDP panel fitter is outside the always-on well. */
- if (dev_priv->pch_pf_size)
- enable = true;
-
intel_set_power_well(dev, enable);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 38b3fb549bac..83d2241176d8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -721,7 +721,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
- struct drm_display_mode *mode = &pipe_config->requested_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_crtc *intel_crtc = encoder->new_crtc;
struct intel_connector *intel_connector = intel_dp->attached_connector;
@@ -744,9 +743,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_gmch_panel_fitting(intel_crtc, pipe_config,
intel_connector->panel.fitting_mode);
else
- intel_pch_panel_fitting(dev,
- intel_connector->panel.fitting_mode,
- mode, adjusted_mode);
+ intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_connector->panel.fitting_mode);
}
/* We need to take the panel's fixed mode into account. */
target_clock = adjusted_mode->clock;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1780f79e1a89..6edab480f6b4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -239,7 +239,16 @@ struct intel_crtc_config {
unsigned pixel_multiplier;
/* Panel fitter controls for gen2-gen4 + VLV */
- u32 pfit_control, pfit_pgm_ratios;
+ struct {
+ u32 control;
+ u32 pgm_ratios;
+ } gmch_pfit;
+
+ /* Panel fitter placement and size for Ironlake+ */
+ struct {
+ u32 pos;
+ u32 size;
+ } pch_pfit;
};
struct intel_crtc {
@@ -558,10 +567,9 @@ extern void intel_panel_fini(struct intel_panel *panel);
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
-extern void intel_pch_panel_fitting(struct drm_device *dev,
- int fitting_mode,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode);
+extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config,
+ int fitting_mode);
extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config,
int fitting_mode);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2a2180410cbd..d125756a2665 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -229,7 +229,6 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
struct intel_connector *intel_connector =
&lvds_encoder->attached_connector->base;
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
- struct drm_display_mode *mode = &pipe_config->requested_mode;
struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
unsigned int lvds_bpp;
int pipe;
@@ -267,9 +266,8 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (HAS_PCH_SPLIT(dev)) {
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(dev,
- intel_connector->panel.fitting_mode,
- mode, adjusted_mode);
+ intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_connector->panel.fitting_mode);
return true;
} else {
intel_gmch_panel_fitting(intel_crtc, pipe_config,
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index b775dd5f8dd9..5cd82a5ce907 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -54,14 +54,17 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
/* adjusted_mode has been preset to be the panel's fixed mode */
void
-intel_pch_panel_fitting(struct drm_device *dev,
- int fitting_mode,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
+ struct intel_crtc_config *pipe_config,
+ int fitting_mode)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+ struct drm_display_mode *mode, *adjusted_mode;
int x, y, width, height;
+ mode = &pipe_config->requested_mode;
+ adjusted_mode = &pipe_config->adjusted_mode;
+
x = y = width = height = 0;
/* Native modes don't need fitting */
@@ -113,8 +116,8 @@ intel_pch_panel_fitting(struct drm_device *dev,
}
done:
- dev_priv->pch_pf_pos = (x << 16) | y;
- dev_priv->pch_pf_size = (width << 16) | height;
+ pipe_config->pch_pfit.pos = (x << 16) | y;
+ pipe_config->pch_pfit.size = (width << 16) | height;
}
static void
@@ -300,10 +303,10 @@ out:
if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
- if (pfit_control != pipe_config->pfit_control ||
- pfit_pgm_ratios != pipe_config->pfit_pgm_ratios) {
- pipe_config->pfit_control = pfit_control;
- pipe_config->pfit_pgm_ratios = pfit_pgm_ratios;
+ if (pfit_control != pipe_config->gmch_pfit.control ||
+ pfit_pgm_ratios != pipe_config->gmch_pfit.pgm_ratios) {
+ pipe_config->gmch_pfit.control = pfit_control;
+ pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
}
dev_priv->lvds_border_bits = border;
}
--
1.8.5.rc3