| From beb91f82dc8961b39bb0a815ef62d2db08777ed4 Mon Sep 17 00:00:00 2001 |
| From: Ben Widawsky <ben@bwidawsk.net> |
| Date: Tue, 23 Apr 2013 23:15:30 -0700 |
| Subject: drm/i915: BUG_ON bad PPGTT offset |
| |
| Because PPGTT PDEs within the GTT are calculated in cachelines |
| (HW guys consistency ftw) we do a divide which will wreak havoc if this |
| is wrong, and I know that from experience). |
| |
| If/when we move to multiple PPGTTs this will have to become a WARN, and |
| return an error. For now however it should always be considered fatal, |
| and only a developer could hit it. |
| |
| Signed-off-by: Ben Widawsky <ben@bwidawsk.net> |
| Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> |
| [danvet: s/BUG/WARN] |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| |
| (cherry picked from commit 0a73287060cdd8fc2b50ecd216c918c2d097de59) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c |
| index de6e7c54ea56..a22e22cfd105 100644 |
| --- a/drivers/gpu/drm/i915/i915_gem_gtt.c |
| +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c |
| @@ -110,6 +110,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev) |
| uint32_t pd_entry; |
| int i; |
| |
| + WARN_ON(ppgtt->pd_offset & 0x3f); |
| + |
| pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
| ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); |
| for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| -- |
| 1.8.5.rc3 |
| |
