| From 412c0089d9c529c571dc103885b206841d856db9 Mon Sep 17 00:00:00 2001 |
| From: Jesse Barnes <jbarnes@virtuousgeek.org> |
| Date: Thu, 2 May 2013 10:48:09 -0700 |
| Subject: drm/i915: set proper DPIO post divider for VGA on VLV v4 |
| |
| Supposedly we should use the DAC divider for <300MHz pixel clocks, but as |
| that doesn't actually work as well as the high freq divider here in |
| practice, just use the high freq divider all the time. |
| |
| v2: remove unconditional write (Jesse) |
| check for pixel rate properly (Jesse) |
| v3: give up, the DAC divider apparently doesn't work, and low res modes |
| work ok (Jesse) |
| remove debug msg (Jesse) |
| |
| Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> |
| Tested-by: Kenneth Graunke <kenneth@whitecape.org> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 7df5080bc7f3e3fba9cddac71133ed52864c40be) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 11 +++++++---- |
| 1 file changed, 7 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c |
| index 745bcca57db6..b13dc43725da 100644 |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -4474,10 +4474,13 @@ static void vlv_update_pll(struct intel_crtc *crtc) |
| mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| mdiv |= ((bestn << DPIO_N_SHIFT)); |
| mdiv |= (1 << DPIO_K_SHIFT); |
| - if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) || |
| - intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
| - intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
| - mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
| + |
| + /* |
| + * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| + * but we don't support that). |
| + * Note: don't use the DAC post divider as it seems unstable. |
| + */ |
| + mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
| intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
| |
| mdiv |= DPIO_ENABLE_CALIBRATION; |
| -- |
| 1.8.5.rc3 |
| |