| From 1942bc78fa200b14c821f42f57114f48fabbe5e7 Mon Sep 17 00:00:00 2001 |
| From: Rodrigo Vivi <rodrigo.vivi@gmail.com> |
| Date: Mon, 6 May 2013 19:37:34 -0300 |
| Subject: drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue |
| MIME-Version: 1.0 |
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| |
| Display register 42000h bit 22 must be set to 1b for the entire time that |
| Frame Buffer Compression is enabled. |
| |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 30ca7c6f97e266d122b03261f75f530d5c83608b) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_pm.c | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c |
| index 5c976e8aba4c..26aabed959fa 100644 |
| --- a/drivers/gpu/drm/i915/intel_pm.c |
| +++ b/drivers/gpu/drm/i915/intel_pm.c |
| @@ -268,6 +268,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
| IVB_DPFC_CTL_FENCE_EN | |
| intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); |
| |
| + /* WaFbcAsynchFlipDisableFbcQueue */ |
| + I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); |
| I915_WRITE(SNB_DPFC_CTL_SA, |
| SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| -- |
| 1.8.5.rc3 |
| |
