| From ad3d17fd1ffb41255af37cbacf0b3602627ece21 Mon Sep 17 00:00:00 2001 |
| From: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Date: Fri, 3 May 2013 17:23:45 -0300 |
| Subject: drm/i915: set FORCE_ARB_IDLE_PLANES workaround |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround |
| inside haswell_init_clock_gating and mentioned it is "a workaround for |
| early silicon revisions and should be removed later". This workaround |
| is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned |
| that setting FORCE_ARB_IDLE_PLANES replaces that workaround for the |
| newer machines. So use the new one. |
| |
| Also notice that there's still another workaround for PRI_CTL that |
| involves WM_DBG, but it's not the one we're reverting. And notice that |
| we were previously setting WM_DBG_DISALLOW_MULTIPIPE_LP which disables |
| the LP watermarks when more than one pipe is used, and we really don't |
| want this because we need the LP watermarks if we want to reach deeper |
| PC states. |
| |
| Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| [danvet: Add a comment for the w/a name Ville dug out of Bspec.] |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| |
| (cherry picked from commit 90a8864320b2a9f91e5b5d561924a4bb70b90dcc) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 3 +++ |
| drivers/gpu/drm/i915/intel_pm.c | 11 +++-------- |
| 2 files changed, 6 insertions(+), 8 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -3723,6 +3723,9 @@ |
| # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
| # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) |
| |
| +#define CHICKEN_PAR1_1 0x42080 |
| +#define FORCE_ARB_IDLE_PLANES (1 << 14) |
| + |
| #define DISP_ARB_CTL 0x45000 |
| #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
| #define DISP_FBC_WM_DIS (1<<15) |
| --- a/drivers/gpu/drm/i915/intel_pm.c |
| +++ b/drivers/gpu/drm/i915/intel_pm.c |
| @@ -4172,14 +4172,9 @@ static void haswell_init_clock_gating(st |
| /* WaSwitchSolVfFArbitrationPriority:hsw */ |
| I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| |
| - /* XXX: This is a workaround for early silicon revisions and should be |
| - * removed later. |
| - */ |
| - I915_WRITE(WM_DBG, |
| - I915_READ(WM_DBG) | |
| - WM_DBG_DISALLOW_MULTIPLE_LP | |
| - WM_DBG_DISALLOW_SPRITE | |
| - WM_DBG_DISALLOW_MAXFIFO); |
| + /* WaRsPkgCStateDisplayPMReq:hsw */ |
| + I915_WRITE(CHICKEN_PAR1_1, |
| + I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
| |
| lpt_init_clock_gating(dev); |
| } |
