blob: 4559afe413edb1e8582cc946f67cef6e45bb61a4 [file] [log] [blame]
From c9a4f9452c674a864b7e27fccf1e977d1bb84bc4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Tue, 4 Jun 2013 13:48:59 +0300
Subject: drm/i915: Always load the display palette before enabling the pipe
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Loading the palette after the planes are enabled can risk showing
incorrect colors. ILK+ already load the palette before even the pipe
is enabled. Just follow the same order for gen2-4 and VLV.
According to BSpec the requirements for palette access are
display core clock and display PLL running. In certain platforms
just the core clock may be enough. But we definitely should have both
running when this gets called during the modeset.
v2: Amend the commit message with some display PLL/core clock info
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 63cbb0747622d923665294519e9a24bc9c654c19)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7bd619db7cd6..885aa16b74f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3618,10 +3618,11 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
/* Enable panel fitting for eDP */
i9xx_pfit_enable(intel_crtc);
+ intel_crtc_load_lut(crtc);
+
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
- intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
/* Give the overlay scaler a chance to enable if it's on this pipe */
@@ -3657,12 +3658,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
/* Enable panel fitting for LVDS */
i9xx_pfit_enable(intel_crtc);
+ intel_crtc_load_lut(crtc);
+
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
if (IS_G4X(dev))
g4x_fixup_plane(dev_priv, pipe);
- intel_crtc_load_lut(crtc);
intel_update_fbc(dev);
/* Give the overlay scaler a chance to enable if it's on this pipe */
--
1.8.5.rc3