| From 43b399b96c042230cccacac01e533d1e2464977f Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Tue, 4 Jun 2013 13:49:07 +0300 |
| Subject: drm/i915: Assert dpll running in intel_crtc_load_lut() on pre-PCH |
| platforms |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Adding more context from Ville's reply to Rodrigo's question why we |
| need this: |
| |
| "The spec says that on some hardware you need to PLL running before you |
| can poke at the palette registers. I didn't actually try to anger the |
| hardware so I'm not really sure what would happen otherwise, but IIRC |
| Jesse said something about a hard system hang..." |
| |
| And generally documenting such ordering constraints with asserts is |
| Just Good. |
| |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> |
| [danvet: Spruce up the commit message a lot.] |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| |
| (cherry picked from commit 14420bd0065c1757a353e36ebc9cc4bdc6932dcd) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 3 +++ |
| 1 file changed, 3 insertions(+) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c |
| index 54208ba52894..63ff08834209 100644 |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -6311,6 +6311,9 @@ void intel_crtc_load_lut(struct drm_crtc *crtc) |
| if (!crtc->enabled || !intel_crtc->active) |
| return; |
| |
| + if (!HAS_PCH_SPLIT(dev_priv->dev)) |
| + assert_pll_enabled(dev_priv, pipe); |
| + |
| /* use legacy palette for Ironlake */ |
| if (HAS_PCH_SPLIT(dev)) |
| palreg = LGC_PALETTE(pipe); |
| -- |
| 1.8.5.rc3 |
| |
