| From 214ac6d59b698fa49712b1592dcac43de38d8bc7 Mon Sep 17 00:00:00 2001 |
| From: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Date: Wed, 5 Jun 2013 13:34:15 +0200 |
| Subject: drm/i915: drop crtc checking from assert_shared_dpll |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| The hw state readout code for the pipe config will now check |
| this for us, so rip out this hand-rolled complexity. |
| |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit e9d6944ed75dbf16ae34bb73bd1eeca7cb183b67) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 35 +++++++---------------------------- |
| 1 file changed, 7 insertions(+), 28 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c |
| index 4dd9e134f687..f29c8a4477da 100644 |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -923,7 +923,6 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
| /* For ILK+ */ |
| static void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| struct intel_shared_dpll *pll, |
| - struct intel_crtc *crtc, |
| bool state) |
| { |
| u32 val; |
| @@ -943,28 +942,9 @@ static void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| WARN(cur_state != state, |
| "%s assertion failure (expected %s, current %s), val=%08x\n", |
| pll->name, state_string(state), state_string(cur_state), val); |
| - |
| - /* Make sure the selected PLL is correctly attached to the transcoder */ |
| - if (crtc && HAS_PCH_CPT(dev_priv->dev)) { |
| - u32 pch_dpll; |
| - |
| - pch_dpll = I915_READ(PCH_DPLL_SEL); |
| - cur_state = pll->id == DPLL_ID_PCH_PLL_B; |
| - if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, |
| - "PLL[%d] not attached to this transcoder %c: %08x\n", |
| - cur_state, pipe_name(crtc->pipe), pch_dpll)) { |
| - cur_state = !!(val >> (4*crtc->pipe + 3)); |
| - WARN(cur_state != state, |
| - "PLL[%d] not %s on this transcoder %c: %08x\n", |
| - pll->id == DPLL_ID_PCH_PLL_B, |
| - state_string(state), |
| - pipe_name(crtc->pipe), |
| - val); |
| - } |
| - } |
| } |
| -#define assert_shared_dpll_enabled(d, p, c) assert_shared_dpll(d, p, c, true) |
| -#define assert_shared_dpll_disabled(d, p, c) assert_shared_dpll(d, p, c, false) |
| +#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| +#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| |
| static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| enum pipe pipe, bool state) |
| @@ -1434,7 +1414,7 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
| |
| if (pll->active++) { |
| WARN_ON(!pll->on); |
| - assert_shared_dpll_enabled(dev_priv, pll, NULL); |
| + assert_shared_dpll_enabled(dev_priv, pll); |
| return; |
| } |
| WARN_ON(pll->on); |
| @@ -1462,11 +1442,11 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
| crtc->base.base.id); |
| |
| if (WARN_ON(pll->active == 0)) { |
| - assert_shared_dpll_disabled(dev_priv, pll, NULL); |
| + assert_shared_dpll_disabled(dev_priv, pll); |
| return; |
| } |
| |
| - assert_shared_dpll_enabled(dev_priv, pll, NULL); |
| + assert_shared_dpll_enabled(dev_priv, pll); |
| WARN_ON(!pll->on); |
| if (--pll->active) |
| return; |
| @@ -1489,8 +1469,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| |
| /* Make sure PCH DPLL is enabled */ |
| assert_shared_dpll_enabled(dev_priv, |
| - intel_crtc_to_shared_dpll(intel_crtc), |
| - intel_crtc); |
| + intel_crtc_to_shared_dpll(intel_crtc)); |
| |
| /* FDI must be feeding us bits for PCH ports */ |
| assert_fdi_tx_enabled(dev_priv, pipe); |
| @@ -3112,7 +3091,7 @@ found: |
| if (pll->active == 0) { |
| DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| WARN_ON(pll->on); |
| - assert_shared_dpll_disabled(dev_priv, pll, NULL); |
| + assert_shared_dpll_disabled(dev_priv, pll); |
| |
| /* Wait for the clocks to stabilize before rewriting the regs */ |
| I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE); |
| -- |
| 1.8.5.rc3 |
| |