blob: b4e02d98c1f575a70d2f709b17e439f7d26102d3 [file] [log] [blame]
From 1da5d6aeb2f6038bd908c8e30de516b4d1989151 Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Tue, 21 May 2013 21:54:55 +0200
Subject: drm/i915: pnv dpll doesn't use m1!
So don't try to store it in the DPLL_FP register.
Otherwise it looks like the limits for pineview are correct: It has
it's own clock computation code, which doesn't use an offset for n
divisors, and the register value based m limits look sane enough.
v2: Rebase on top of the pineview clock refactor and fixup up the
commit message: It's m1 pnv doens't care about, not m2!
Quoting Damien's review:
- "n can vary between 2 and 6, but we declare the 3-6 as limits.
- "p1 seems to be able to go up to 9
- "the m upper limit seems a bit big, but the docs are a bit shy on
that values for pnv.
"Otherwise, the change itself seems good:"
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 7df00d7adb080122502a30ec48f237d2f90d36ad)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f29c8a4477da..e21c1466a97d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4236,7 +4236,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
{
- return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
+ return (1 << dpll->n) << 16 | dpll->m2;
}
static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
--
1.8.5.rc3