blob: af4a1fb881dab465400bbdb488f5f75eac672664 [file] [log] [blame]
From eedf76facbe0527aa8201e52d661005bbc36b3bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <>
Date: Wed, 12 Jun 2013 22:11:18 +0300
Subject: drm/i915: Try harder to disable trickle feed on VLV
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The specs are a bit unclear whether the per-plane trickle feed disable
control exists on VLV. There is another trickle feed disable control
in the MI_ARB register.
After some experimentation it turns out both the DSPCNTR trickle feed
bits and the MI_ARB bit can be toggled. However the DSPCNTR bits don't
seem to have any effect.
The MI_ARB bit, on the other hand, has a noticable effect. I performed
an experiment where I reduced the FIFO size via DSPARB and observed the
effect of the MI_ARB trickle feed bit on the display.
Using a 1920x1080-60 mode, with MI_ARB=0x4 the display started to have
problems with DSPARB=0x42424242, whereas with MI_ARB=0x0 the problems
didn't start until DSPARB=0x09090909. This seems to confirm that the
MI_ARB trickle feed bit actually does work.
So replace the use of the DSPCNTR trickle feed bits with MI_ARB
on VLV.
v2: Amend commit message with results from experimentation
Signed-off-by: Ville Syrjälä <>
Reviewed-by: Jesse Barnes <>
Signed-off-by: Daniel Vetter <>
(cherry picked from commit e0d8d59b0831523da61739c9d5e3bc3c77d7b5db)
Signed-off-by: Darren Hart <>
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1371,6 +1371,8 @@
#define FW_CSPWRDWNEN (1<<15)
+#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
* Palette regs
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4873,7 +4873,7 @@ static void valleyview_init_clock_gating
- g4x_disable_trickle_feed(dev);