| From 0c4b34c049b3ff05e65bd2f75ddafb84365d8b8f Mon Sep 17 00:00:00 2001 |
| From: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Date: Thu, 4 Jul 2013 23:35:30 +0200 |
| Subject: drm/i915: don't enable PM_VEBOX_CS_ERROR_INTERRUPT |
| |
| The code to handle it is broken - there's simply no code to clear CS |
| parser errors on gen5+. And behold, for all the other rings we also |
| don't enable it! |
| |
| Leave the handling code itself in place just to be consistent with the |
| existing mess though. And in case someone feels like fixing it all up. |
| |
| This has been errornously enabled in |
| |
| commit 12638c57f31952127c734c26315e1348fa1334c2 |
| Author: Ben Widawsky <ben@bwidawsk.net> |
| Date: Tue May 28 19:22:31 2013 -0700 |
| |
| drm/i915: Enable vebox interrupts |
| |
| Cc: Damien Lespiau <damien.lespiau@intel.com> |
| Cc: Ben Widawsky <ben@bwidawsk.net> |
| Reviewed-by: Ben Widawsky <ben@bwidawsk.net> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit c0d6a3dd61d46a640ead0a9d38b78ca22d37a304) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_irq.c | 3 +-- |
| drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +-- |
| 2 files changed, 2 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_irq.c |
| +++ b/drivers/gpu/drm/i915/i915_irq.c |
| @@ -2860,8 +2860,7 @@ static int ivybridge_irq_postinstall(str |
| |
| I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
| if (HAS_VEBOX(dev)) |
| - pm_irqs |= PM_VEBOX_USER_INTERRUPT | |
| - PM_VEBOX_CS_ERROR_INTERRUPT; |
| + pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| |
| /* Our enable/disable rps functions may touch these registers so |
| * make sure to set a known state for only the non-RPS bits. |
| --- a/drivers/gpu/drm/i915/intel_ringbuffer.c |
| +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c |
| @@ -2030,8 +2030,7 @@ int intel_init_vebox_ring_buffer(struct |
| ring->add_request = gen6_add_request; |
| ring->get_seqno = gen6_ring_get_seqno; |
| ring->set_seqno = ring_set_seqno; |
| - ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT | |
| - PM_VEBOX_CS_ERROR_INTERRUPT; |
| + ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| ring->irq_get = hsw_vebox_get_irq; |
| ring->irq_put = hsw_vebox_put_irq; |
| ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
