| From 6b30fedf8f6c31c1a0744fad8b10d0c0894cb114 Mon Sep 17 00:00:00 2001 |
| From: Ben Widawsky <ben@bwidawsk.net> |
| Date: Thu, 4 Jul 2013 11:02:04 -0700 |
| Subject: drm/i915: Define some of the eLLC magic |
| |
| The EDRAM present register isn't really defined in the docs. It just |
| says check to see if it's set to 1. So I haven't defined the 1 value not |
| knowing what it actually means. |
| |
| Signed-off-by: Ben Widawsky <ben@bwidawsk.net> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 05e21cc43da5a1a58b34a2cfad13d22bcfeb1f2b) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_gem.c | 4 ++-- |
| drivers/gpu/drm/i915/i915_reg.h | 4 ++++ |
| 2 files changed, 6 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_gem.c |
| +++ b/drivers/gpu/drm/i915/i915_gem.c |
| @@ -4131,8 +4131,8 @@ i915_gem_init_hw(struct drm_device *dev) |
| if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| return -EIO; |
| |
| - if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
| - I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); |
| + if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) |
| + I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
| |
| if (HAS_PCH_NOP(dev)) { |
| u32 temp = I915_READ(GEN7_MSG_CTL); |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -4486,6 +4486,10 @@ |
| #define GT_FIFO_FREE_ENTRIES 0x120008 |
| #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
| |
| +#define HSW_IDICR 0x9008 |
| +#define IDIHASHMSK(x) (((x) & 0x3f) << 16) |
| +#define HSW_EDRAM_PRESENT 0x120010 |
| + |
| #define GEN6_UCGCTL1 0x9400 |
| # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
