| From 23cd4eb0e4a3c1048ff92f0bace88a60e12c3459 Mon Sep 17 00:00:00 2001 |
| From: Chris Wilson <chris@chris-wilson.co.uk> |
| Date: Fri, 19 Jul 2013 20:36:54 +0100 |
| Subject: drm/i915: Use the common register access functions for NOTRACE |
| variants |
| |
| Detangle the confusion that NOTRACE variants of the register read/write |
| routines were directly using the raw register access. We need for those |
| routines to reuse the common code for serializing register access and |
| ensuring the correct register power states. This is only possible now |
| that the only routines that required raw access use their own API. |
| |
| Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit dba8e41f2be04de58eadf78f524b3f981bf438c2) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_drv.h | 28 ++++++++++++++-------------- |
| drivers/gpu/drm/i915/intel_uncore.c | 8 ++++---- |
| 2 files changed, 18 insertions(+), 18 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h |
| index ababee4f2f2e..2f8699b03722 100644 |
| --- a/drivers/gpu/drm/i915/i915_drv.h |
| +++ b/drivers/gpu/drm/i915/i915_drv.h |
| @@ -2135,7 +2135,7 @@ int vlv_gpu_freq(int ddr_freq, int val); |
| int vlv_freq_opcode(int ddr_freq, int val); |
| |
| #define __i915_read(x) \ |
| - u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
| + u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace); |
| __i915_read(8) |
| __i915_read(16) |
| __i915_read(32) |
| @@ -2143,28 +2143,28 @@ __i915_read(64) |
| #undef __i915_read |
| |
| #define __i915_write(x) \ |
| - void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
| + void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace); |
| __i915_write(8) |
| __i915_write(16) |
| __i915_write(32) |
| __i915_write(64) |
| #undef __i915_write |
| |
| -#define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
| -#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
| +#define I915_READ8(reg) i915_read8(dev_priv, (reg), true) |
| +#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true) |
| |
| -#define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
| -#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
| -#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
| -#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
| +#define I915_READ16(reg) i915_read16(dev_priv, (reg), true) |
| +#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true) |
| +#define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false) |
| +#define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false) |
| |
| -#define I915_READ(reg) i915_read32(dev_priv, (reg)) |
| -#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
| -#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
| -#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
| +#define I915_READ(reg) i915_read32(dev_priv, (reg), true) |
| +#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true) |
| +#define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false) |
| +#define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false) |
| |
| -#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
| -#define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
| +#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true) |
| +#define I915_READ64(reg) i915_read64(dev_priv, (reg), true) |
| |
| #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c |
| index 228bc7a3f373..2dcf682d8dad 100644 |
| --- a/drivers/gpu/drm/i915/intel_uncore.c |
| +++ b/drivers/gpu/drm/i915/intel_uncore.c |
| @@ -343,7 +343,7 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| } |
| |
| #define __i915_read(x) \ |
| -u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| +u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace) { \ |
| unsigned long irqflags; \ |
| u##x val = 0; \ |
| spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
| @@ -359,7 +359,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
| val = __raw_i915_read##x(dev_priv, reg); \ |
| } \ |
| spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| - trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| + if (trace) trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
| return val; \ |
| } |
| |
| @@ -370,10 +370,10 @@ __i915_read(64) |
| #undef __i915_read |
| |
| #define __i915_write(x) \ |
| -void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
| +void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace) { \ |
| unsigned long irqflags; \ |
| u32 __fifo_ret = 0; \ |
| - trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| + if (trace) trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
| spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
| if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| -- |
| 1.8.5.rc3 |
| |
