blob: 4f0ea74d35b012252d80b2482725a2b1d3fbfd1d [file] [log] [blame]
From 00b87c74b30ace16d028aeb50796d7101086cf09 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Fri, 5 Jul 2013 11:57:19 +0300
Subject: drm/i915: Don't pass "mem_value" to ilk_compute_fbc_wm
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The FBC watermark doesn't depend on the latency value, so no point in
passing it in.
Note: It actually depends upon the latency, but only through priv_val
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Add review comment from Paulo to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 1fda9882ca0ba134134c5bf04b8d4f4f06b52649)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2842614bf76..573c13c3046e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2260,8 +2260,7 @@ static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
/* Only for WM_LP. */
static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
- uint32_t pri_val,
- uint32_t mem_value)
+ uint32_t pri_val)
{
if (!params->active)
return 0;
@@ -2284,7 +2283,7 @@ static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
pri_val[pipe] = ilk_compute_pri_wm(p, mem_value, true);
spr_val[pipe] = ilk_compute_spr_wm(p, mem_value);
cur_val[pipe] = ilk_compute_cur_wm(p, mem_value);
- fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe], mem_value);
+ fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
}
result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
--
1.8.5.rc3