blob: c9c23f0545e09abb883bac4f5907849e6f8cbcc6 [file] [log] [blame]
From bd601bcf434dbc2cb43751f507e24a0163401c62 Mon Sep 17 00:00:00 2001
From: Imre Deak <>
Date: Tue, 30 Jul 2013 13:36:32 +0300
Subject: drm/i915: make user mode sync polarity setting explicit
Userspace can pass a mode with an unspecified vsync/hsync polarity
setting. All encoders in the Intel driver take this to mean a negative
polarity setting. The HW readout/state checker code on the other hand
needs these flags to be explicitly set, otherwise the state checker will
WARN about the mismatch.
Get rid of the WARN by making the polarity setting explicit in the
adjusted mode flags based on the requested mode flags. This will keep
the existing behavior otherwise.
Note that we could guess from the other timing parameters whether the
user wanted a VESA or other standard mode and set the polarity
accordingly. This is what the NV driver does
(drivers/gpu/drm/nouveau/dispnv04/crtc.c), but I think that's not very
exact and would change the existing behavior of the Intel driver.
Signed-off-by: Imre Deak <>
Tested-by: cancan,feng <>
Reviewed-by: Chris Wilson <>
Signed-off-by: Daniel Vetter <>
(cherry picked from commit 2960bc9cceecb5d556ce1c07656a6609e2f7e8b0)
Signed-off-by: Darren Hart <>
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41ce30eac8ec..bd3591af3395 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8065,6 +8065,19 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
(enum transcoder) to_intel_crtc(crtc)->pipe;
pipe_config->shared_dpll = DPLL_ID_PRIVATE;
+ /*
+ * Sanitize sync polarity flags based on requested ones. If neither
+ * positive or negative polarity is requested, treat this as meaning
+ * negative polarity.
+ */
+ if (!(pipe_config->adjusted_mode.flags &
+ pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+ if (!(pipe_config->adjusted_mode.flags &
+ pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
/* Compute a starting value for pipe_config->pipe_bpp taking the source
* plane pixel format and any sink constraints into account. Returns the
* source plane bpp so that dithering can be selected on mismatches