blob: 8d588d14e85365ce9046d06d9cde45a8afcc6438 [file] [log] [blame]
From 4af7854549457ba7c912431bdcf59b78baa56700 Mon Sep 17 00:00:00 2001
From: Ben Widawsky <>
Date: Mon, 12 Aug 2013 16:53:03 -0700
Subject: drm/i915: Initialize seqno for VECS too
We require n-1 mailboxes for proper semaphore synchronization. All
semaphore synchronization code relies on proper values in these
mailboxes. The fact that we failed to touch the vebox ring by itself
was unlikely to be an issue since the HW should be initializing the
values to 0. However the error framework for testing seqno wrap
introduced by Mika, in addition to the hangcheck via seqno, and
i915_error_first_batchbuffer() combined caused a nice explosion.
The problem is caused by seqno wrap because the wrap condition is not
properly setup. The wrap code attempts to set the sync mailboxes all
to 0, and then set the current seqno to one less than 0. In all cases,
the vebox mailbox wasn't properly being initialized. This caused a
wrap to not occur. When hangcheck kicks in with the bogus seqno
values, the rest just doesn't work. It makes me wonder if we shouldn't
consider a dumber version of hangcheck...
How we messed this up: VECS support was written before the
aforementioned other features. Upon VECS being rebased, these facts
were missed.
Cc: Mika Kuoppala <>
Signed-off-by: Ben Widawsky <>
Signed-off-by: Daniel Vetter <>
(cherry picked from commit 5020150b3b8d2912466e28572f25b3cc56722aec)
Signed-off-by: Darren Hart <>
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1616,6 +1616,8 @@ void intel_ring_init_seqno(struct intel_
if (INTEL_INFO(ring->dev)->gen >= 6) {
I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
+ if (HAS_VEBOX(ring->dev))
+ I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
ring->set_seqno(ring, seqno);