| From 72c858663ac200d764a873bcbfce8eae135d2e77 Mon Sep 17 00:00:00 2001 |
| From: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Date: Fri, 23 Aug 2013 19:51:28 -0300 |
| Subject: drm/i915: enable trickle feed on Haswell |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| We shouldn't disable the trickle feed bits on Haswell. Our |
| documentation explicitly says the trickle feed bits of PRI_CTL and |
| CUR_CTL should not be programmed to 1, and the hardware engineer also |
| asked us to not program the SPR_CTL field to 1. Leaving the bits as 1 |
| could cause underflows. |
| |
| Reported-by: Arthur Runyan <arthur.j.runyan@intel.com> |
| Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 1f5d76dbb636c73912c9ff1c90ff46dd2273f098) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 1 + |
| drivers/gpu/drm/i915/intel_display.c | 10 +++++++--- |
| drivers/gpu/drm/i915/intel_pm.c | 2 -- |
| drivers/gpu/drm/i915/intel_sprite.c | 7 +++++-- |
| 4 files changed, 13 insertions(+), 7 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -3319,6 +3319,7 @@ |
| #define MCURSOR_PIPE_A 0x00 |
| #define MCURSOR_PIPE_B (1 << 28) |
| #define MCURSOR_GAMMA_ENABLE (1 << 26) |
| +#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
| #define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084) |
| #define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088) |
| #define CURSOR_POS_MASK 0x007FF |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -2077,8 +2077,10 @@ static int ironlake_update_plane(struct |
| else |
| dspcntr &= ~DISPPLANE_TILED; |
| |
| - /* must disable */ |
| - dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| + if (IS_HASWELL(dev)) |
| + dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
| + else |
| + dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| |
| I915_WRITE(reg, dspcntr); |
| |
| @@ -6764,8 +6766,10 @@ static void ivb_update_cursor(struct drm |
| cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| cntl |= CURSOR_MODE_DISABLE; |
| } |
| - if (IS_HASWELL(dev)) |
| + if (IS_HASWELL(dev)) { |
| cntl |= CURSOR_PIPE_CSC_ENABLE; |
| + cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
| + } |
| I915_WRITE(CURCNTR_IVB(pipe), cntl); |
| |
| intel_crtc->cursor_visible = visible; |
| --- a/drivers/gpu/drm/i915/intel_pm.c |
| +++ b/drivers/gpu/drm/i915/intel_pm.c |
| @@ -4960,8 +4960,6 @@ static void haswell_init_clock_gating(st |
| I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| |
| - g4x_disable_trickle_feed(dev); |
| - |
| /* WaVSRefCountFullforceMissDisable:hsw */ |
| gen7_setup_fixed_func_scheduler(dev_priv); |
| |
| --- a/drivers/gpu/drm/i915/intel_sprite.c |
| +++ b/drivers/gpu/drm/i915/intel_sprite.c |
| @@ -260,8 +260,11 @@ ivb_update_plane(struct drm_plane *plane |
| if (obj->tiling_mode != I915_TILING_NONE) |
| sprctl |= SPRITE_TILED; |
| |
| - /* must disable */ |
| - sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
| + if (IS_HASWELL(dev)) |
| + sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
| + else |
| + sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
| + |
| sprctl |= SPRITE_ENABLE; |
| |
| if (IS_HASWELL(dev)) |
