| From 0287a337d790db1b887b28bc97ddbbee14bdccd5 Mon Sep 17 00:00:00 2001 |
| From: Jani Nikula <jani.nikula@intel.com> |
| Date: Fri, 6 Sep 2013 07:38:29 +0300 |
| Subject: drm/i915: name intel dp hooks per platform |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| In line with the rest of the code base. No functional changes. |
| |
| v2: also s/intel_pre_enable_dp/g4x_pre_enable_dp/ for consistency (Ville) |
| |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit ecff4f3bafaf4ce814b491f580bdc1221b07a85b) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++-------- |
| 1 file changed, 10 insertions(+), 8 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/intel_dp.c |
| +++ b/drivers/gpu/drm/i915/intel_dp.c |
| @@ -1731,11 +1731,16 @@ static void intel_enable_dp(struct intel |
| ironlake_edp_backlight_on(intel_dp); |
| } |
| |
| +static void g4x_enable_dp(struct intel_encoder *encoder) |
| +{ |
| + intel_enable_dp(encoder); |
| +} |
| + |
| static void vlv_enable_dp(struct intel_encoder *encoder) |
| { |
| } |
| |
| -static void intel_pre_enable_dp(struct intel_encoder *encoder) |
| +static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
| { |
| struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| @@ -1775,7 +1780,7 @@ static void vlv_pre_enable_dp(struct int |
| vlv_wait_port_ready(dev_priv, port); |
| } |
| |
| -static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) |
| +static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| { |
| struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| struct drm_device *dev = encoder->base.dev; |
| @@ -1785,9 +1790,6 @@ static void intel_dp_pre_pll_enable(stru |
| int port = vlv_dport_to_channel(dport); |
| int pipe = intel_crtc->pipe; |
| |
| - if (!IS_VALLEYVIEW(dev)) |
| - return; |
| - |
| /* Program Tx lane resets to default */ |
| mutex_lock(&dev_priv->dpio_lock); |
| vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), |
| @@ -3576,12 +3578,12 @@ intel_dp_init(struct drm_device *dev, in |
| intel_encoder->get_hw_state = intel_dp_get_hw_state; |
| intel_encoder->get_config = intel_dp_get_config; |
| if (IS_VALLEYVIEW(dev)) { |
| - intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable; |
| + intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
| intel_encoder->pre_enable = vlv_pre_enable_dp; |
| intel_encoder->enable = vlv_enable_dp; |
| } else { |
| - intel_encoder->pre_enable = intel_pre_enable_dp; |
| - intel_encoder->enable = intel_enable_dp; |
| + intel_encoder->pre_enable = g4x_pre_enable_dp; |
| + intel_encoder->enable = g4x_enable_dp; |
| } |
| |
| intel_dig_port->port = port; |