| From 090eb2d0029ac3652631edebefe87e9ef01c911b Mon Sep 17 00:00:00 2001 |
| From: Ben Widawsky <benjamin.widawsky@intel.com> |
| Date: Wed, 11 Sep 2013 14:57:48 -0700 |
| Subject: drm/i915: Synchronize pread/pwrite with wait_rendering |
| |
| lifted from Daniel: |
| pread/pwrite isn't about the object's domain at all, but purely about |
| synchronizing for outstanding rendering. Replacing the call to |
| set_to_gtt_domain with a wait_rendering would imo improve code |
| readability. Furthermore we could pimp pread to only block for |
| outstanding writes and not for reads. |
| |
| Since you're not the first one to trip over this: Can I volunteer you |
| for a follow-up patch to fix this? |
| |
| v2: Switch the pwrite patch to use \!read_only. This was a typo in the |
| original code. (Chris, Daniel) |
| |
| Recommended-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Signed-off-by: Ben Widawsky <ben@bwidawsk.net> |
| [danvet: Fix up the logic fumble - wait_rendering has a bool readonly |
| paramater, set_to_gtt_domain otoh has bool write. Breakage reported by |
| Jani Nikula, I've double-checked that igt/gem_concurrent_blt/prw-* |
| would have caught this.] |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| |
| (cherry picked from commit 23f54483980cea980af37e436ff4e6701aadce12) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/i915_gem.c | 19 +++++++++---------- |
| 1 file changed, 9 insertions(+), 10 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c |
| index 5b510a3bf3ed..bc85c48e856f 100644 |
| --- a/drivers/gpu/drm/i915/i915_gem.c |
| +++ b/drivers/gpu/drm/i915/i915_gem.c |
| @@ -41,6 +41,9 @@ static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *o |
| static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| bool force); |
| static __must_check int |
| +i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| + bool readonly); |
| +static __must_check int |
| i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| struct i915_address_space *vm, |
| unsigned alignment, |
| @@ -430,11 +433,9 @@ i915_gem_shmem_pread(struct drm_device *dev, |
| * optimizes for the case when the gpu will dirty the data |
| * anyway again before the next pread happens. */ |
| needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
| - if (i915_gem_obj_bound_any(obj)) { |
| - ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| - if (ret) |
| - return ret; |
| - } |
| + ret = i915_gem_object_wait_rendering(obj, true); |
| + if (ret) |
| + return ret; |
| } |
| |
| ret = i915_gem_object_get_pages(obj); |
| @@ -746,11 +747,9 @@ i915_gem_shmem_pwrite(struct drm_device *dev, |
| * optimizes for the case when the gpu will use the data |
| * right away and we therefore have to clflush anyway. */ |
| needs_clflush_after = cpu_write_needs_clflush(obj); |
| - if (i915_gem_obj_bound_any(obj)) { |
| - ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| - if (ret) |
| - return ret; |
| - } |
| + ret = i915_gem_object_wait_rendering(obj, false); |
| + if (ret) |
| + return ret; |
| } |
| /* Same trick applies to invalidate partially written cachelines read |
| * before writing. */ |
| -- |
| 1.8.5.rc3 |
| |
