| From c082195c68ea68f9aa91fb4e7af402c988c64d62 Mon Sep 17 00:00:00 2001 |
| From: Jani Nikula <jani.nikula@intel.com> |
| Date: Tue, 17 Sep 2013 18:33:43 +0300 |
| Subject: drm/i915: do not update cursor in crtc mode set |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| The cursor is disabled before crtc mode set in crtc disable (and we |
| assert this is the case), and enabled afterwards in crtc enable. Do not |
| update it in crtc mode set. |
| |
| On HSW enabling a plane on a disabled pipe may hang the entire system. |
| And there's no good reason for doing it ever, so just don't. |
| |
| v2: Add note about HSW hangs - vsyrjala |
| |
| Cc: stable@vger.kernel.org |
| Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit cc173961a68034c1171a421f0dbed39edfb60880) |
| Signed-off-by: James Ausmus <james.ausmus@intel.com> |
| |
| Conflicts: |
| drivers/gpu/drm/i915/intel_display.c |
| (resolved using rerere from b599c89 ("Merge tag 'v3.12-rc2' into |
| drm-intel-next")) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 11 +---------- |
| 1 file changed, 1 insertion(+), 10 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c |
| index 91e2431c0b7e..56f333ebb706 100644 |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -4932,10 +4932,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
| } |
| } |
| |
| - /* Ensure that the cursor is valid for the new mode before changing... */ |
| - intel_crtc_update_cursor(crtc, true); |
| - |
| - if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) { |
| + if (is_lvds && dev_priv->lvds_downclock_avail) { |
| /* |
| * Ensure we match the reduced clock's P to the target clock. |
| * If the clocks don't match, we can't switch the display clock |
| @@ -5845,9 +5842,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
| intel_crtc->config.dpll.p2 = clock.p2; |
| } |
| |
| - /* Ensure that the cursor is valid for the new mode before changing... */ |
| - intel_crtc_update_cursor(crtc, true); |
| - |
| /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
| if (intel_crtc->config.has_pch_encoder) { |
| fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
| @@ -6398,9 +6392,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
| if (!intel_ddi_pll_mode_set(crtc)) |
| return -EINVAL; |
| |
| - /* Ensure that the cursor is valid for the new mode before changing... */ |
| - intel_crtc_update_cursor(crtc, true); |
| - |
| if (intel_crtc->config.has_dp_encoder) |
| intel_dp_set_m_n(intel_crtc); |
| |
| -- |
| 1.8.5.rc3 |
| |
