| From 19c9e2dfbd8013a5270a2bd617b7d2ad8204026a Mon Sep 17 00:00:00 2001 |
| From: Chon Ming Lee <chon.ming.lee@intel.com> |
| Date: Wed, 25 Sep 2013 15:47:51 +0800 |
| Subject: drm/i915: Fix VLV eDP timing v2 |
| |
| Fix the typo in previous commit for DP 1.62 divisor. |
| drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 |
| |
| v2: sigh, the m1 div is 3. |
| |
| Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org> |
| Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| (cherry picked from commit 58f6e632d5d24f1f510bafccc4c963a06f6a55a8) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/gpu/drm/i915/intel_dp.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c |
| index cf4d2197f9e6..0c98af87eb2e 100644 |
| --- a/drivers/gpu/drm/i915/intel_dp.c |
| +++ b/drivers/gpu/drm/i915/intel_dp.c |
| @@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = { |
| |
| static const struct dp_link_dpll vlv_dpll[] = { |
| { DP_LINK_BW_1_62, |
| - { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } }, |
| + { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
| { DP_LINK_BW_2_7, |
| { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| }; |
| -- |
| 1.8.5.rc3 |
| |
