blob: 87acf988011642c55c8235fc4898a40e39e5172e [file] [log] [blame]
From 04d2d395137801b9ed76fe5c92ac2791986f9fb7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Wed, 9 Oct 2013 17:24:58 +0300
Subject: drm/i915: Rename primary_disabled to primary_enabled
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Let's try to avoid these confusing negated booleans.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 4c445e0ebc648ee42c0d21713b8f76597854d47a)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
4 files changed, 11 insertions(+), 11 deletions(-)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1840,9 +1840,9 @@ static void intel_enable_primary_plane(s
/* If the pipe isn't enabled, we can't pump pixels and may hang */
assert_pipe_enabled(dev_priv, pipe);
- WARN(!intel_crtc->primary_disabled, "Primary plane already enabled\n");
+ WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
- intel_crtc->primary_disabled = false;
+ intel_crtc->primary_enabled = true;
reg = DSPCNTR(plane);
val = I915_READ(reg);
@@ -1870,9 +1870,9 @@ static void intel_disable_primary_plane(
int reg;
u32 val;
- WARN(intel_crtc->primary_disabled, "Primary plane already disabled\n");
+ WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
- intel_crtc->primary_disabled = true;
+ intel_crtc->primary_enabled = false;
reg = DSPCNTR(plane);
val = I915_READ(reg);
@@ -10708,7 +10708,7 @@ static void intel_modeset_readout_hw_sta
&crtc->config);
crtc->base.enabled = crtc->active;
- crtc->primary_disabled = !crtc->active;
+ crtc->primary_enabled = crtc->active;
DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
crtc->base.base.id,
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -321,7 +321,7 @@ struct intel_crtc {
*/
bool active;
bool eld_vld;
- bool primary_disabled; /* is the crtc obscured by a plane? */
+ bool primary_enabled; /* is the primary plane (partially) visible? */
bool lowfreq_avail;
struct intel_overlay *overlay;
struct intel_unpin_work *unpin_work;
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -475,7 +475,7 @@ void intel_update_fbc(struct drm_device
*/
list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
if (intel_crtc_active(tmp_crtc) &&
- !to_intel_crtc(tmp_crtc)->primary_disabled) {
+ to_intel_crtc(tmp_crtc)->primary_enabled) {
if (crtc) {
if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -521,10 +521,10 @@ intel_enable_primary(struct drm_crtc *cr
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int reg = DSPCNTR(intel_crtc->plane);
- if (!intel_crtc->primary_disabled)
+ if (intel_crtc->primary_enabled)
return;
- intel_crtc->primary_disabled = false;
+ intel_crtc->primary_enabled = true;
I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
@@ -553,10 +553,10 @@ intel_disable_primary(struct drm_crtc *c
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int reg = DSPCNTR(intel_crtc->plane);
- if (intel_crtc->primary_disabled)
+ if (!intel_crtc->primary_enabled)
return;
- intel_crtc->primary_disabled = true;
+ intel_crtc->primary_enabled = false;
mutex_lock(&dev->struct_mutex);
if (dev_priv->fbc.plane == intel_crtc->plane)