| From 8d8d36c6aa5a14628cdaa270e0af64a5975a4b78 Mon Sep 17 00:00:00 2001 |
| From: Mika Westerberg <mika.westerberg@linux.intel.com> |
| Date: Wed, 3 Jul 2013 13:25:06 +0300 |
| Subject: spi/pxa2xx: enable DMA on newer Intel LPSS silicon |
| |
| There is an additional bit in the Intel LPSS SPI private registers that |
| needs to be set in order to be able to use DMA with the SPI controller. |
| Enable this as well. |
| |
| Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> |
| Signed-off-by: Mark Brown <broonie@linaro.org> |
| (cherry picked from commit 1de7061253a2742c743f3883f0e73480c9bceee0) |
| Signed-off-by: Darren Hart <dvhart@linux.intel.com> |
| --- |
| drivers/spi/spi-pxa2xx.c | 9 ++++++++- |
| 1 file changed, 8 insertions(+), 1 deletion(-) |
| |
| diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c |
| index 97e23c9fb732..91969629d864 100644 |
| --- a/drivers/spi/spi-pxa2xx.c |
| +++ b/drivers/spi/spi-pxa2xx.c |
| @@ -69,6 +69,8 @@ MODULE_ALIAS("platform:pxa2xx-spi"); |
| #define LPSS_TX_HITHRESH_DFLT 224 |
| |
| /* Offset from drv_data->lpss_base */ |
| +#define GENERAL_REG 0x08 |
| +#define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
| #define SSP_REG 0x0c |
| #define SPI_CS_CONTROL 0x18 |
| #define SPI_CS_CONTROL_SW_MODE BIT(0) |
| @@ -142,8 +144,13 @@ detection_done: |
| __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value); |
| |
| /* Enable multiblock DMA transfers */ |
| - if (drv_data->master_info->enable_dma) |
| + if (drv_data->master_info->enable_dma) { |
| __lpss_ssp_write_priv(drv_data, SSP_REG, 1); |
| + |
| + value = __lpss_ssp_read_priv(drv_data, GENERAL_REG); |
| + value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
| + __lpss_ssp_write_priv(drv_data, GENERAL_REG, value); |
| + } |
| } |
| |
| static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) |
| -- |
| 1.8.5.rc3 |
| |
