blob: 4a3d1b136391aa01105227b072aebf73903021f5 [file] [log] [blame]
From 8ea4c070f29260d8bf2cb6f86bd8c23283c8a8cb Mon Sep 17 00:00:00 2001
From: Mathias Nyman <>
Date: Fri, 13 Sep 2013 17:02:29 +0300
Subject: x86/intel/lpss: Add pin control support to Intel low power subsystem
x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.
At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol
functions such as pin muxing and grouping are possible to add
Signed-off-by: Mathias Nyman <>
Reviewed-by: Mika Westerberg <>
Cc: Rafael J. Wysocki <>
Signed-off-by: Ingo Molnar <>
(cherry picked from commit 0f531431d3de88efb4234d6c0ce22089ec035a38)
Signed-off-by: Darren Hart <>
arch/x86/Kconfig | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -472,11 +472,12 @@ config X86_INTEL_LPSS
bool "Intel Low Power Subsystem Support"
depends on ACPI
+ select PINCTRL
Select to build support for Intel Low Power Subsystem such as
found on Intel Lynxpoint PCH. Selecting this option enables
- things like clock tree (common clock framework) which are needed
- by the LPSS peripheral drivers.
+ things like clock tree (common clock framework) and pincontrol
+ which are needed by the LPSS peripheral drivers.
config X86_RDC321X
bool "RDC R-321x SoC"