blob: cc8c1cf355f2f237dd3b1eefee994357de48cce1 [file] [log] [blame]
From ltsi-dev-bounces@lists.linuxfoundation.org Thu Feb 14 20:37:35 2013
From: Do Quang Thang <dq-thang@jinso.co.jp>
Date: Fri, 15 Feb 2013 13:37:02 +0900
Subject: [PATCH 1/2] sh: clkfwk: bugfix: sh_clk_div_enable() care sh_clk_div_set_rate() if div6
To: ltsi-dev@lists.linuxfoundation.org
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Message-ID: <1360903023-19758-2-git-send-email-dq-thang@jinso.co.jp>
764f4e4e33d18cde4dcaf8a0d860b749c6d6d08b
(sh: clkfwk: Use shared sh_clk_div_enable/disable())
shared enable/disable funcions for div4/div6.
But new sh_clk_div_enable() didn't care sh_clk_div_set_rate()
which is required on div6 clock.
This patch fixes it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
(cherry picked from commit 5a799b824b6046befa7e10107a3d65f40816f645)
Signed-off-by: Do Quang Thang <dq-thang@jinso.co.jp>
---
drivers/sh/clk/cpg.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -126,6 +126,12 @@ static int sh_clk_div_set_rate(struct cl
static int sh_clk_div_enable(struct clk *clk)
{
+ if (clk->div_mask == SH_CLK_DIV6_MSK) {
+ int ret = sh_clk_div_set_rate(clk, clk->rate);
+ if (ret < 0)
+ return ret;
+ }
+
sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
return 0;
}