sme: Fix sign-extension bug in SMCR_EL3 write

To enable the full AArch64 ISA support in streaming SVE mode, we need to
set bit 31 in the SMCR_EL3 system register. However ORing (1 << 31) into
an unsigned long variable will lead to all upper 32 bits becoming 1,
which is not what we want. We are just saved by those bits being RES0,
at least for now.

Explicitly use an unsigned base for the shift, to avoid the sign
extension.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Mark: use 'BIT(31)' rather than '(1U << 31)']
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20221004145152.3020464-1-andre.przywara@arm.com/
1 file changed