)]}'
{
  "commit": "b621b157b42f1fe398520cf499db88aa654c78e2",
  "tree": "fd0737494e69c188dd2b662b50856a772a105895",
  "parents": [
    "785302c1f7b9eceab3b72a8cb3d79eaf526fd2e3"
  ],
  "author": {
    "name": "Anshuman Khandual",
    "email": "anshuman.khandual@arm.com",
    "time": "Fri Jun 06 10:56:02 2025 +0530"
  },
  "committer": {
    "name": "Mark Rutland",
    "email": "mark.rutland@arm.com",
    "time": "Tue Jun 10 18:14:43 2025 +0100"
  },
  "message": "aarch64: Enable access into FEAT_SPE_FDS register from EL2 and below\n\nFEAT_SPE_FDS adds system register PMSDSFR_EL1. But accessing that system\nregister from EL2 and below exception levels, will trap into EL3 unless\nMDCR_EL3.EnPMS3 is set.\n\nEnable access to FEAT_SPE_FDS registers when they are implemented.\n\nCc: James Clark \u003cjames.clark@linaro.org\u003e\nCc: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nReviewed-by: James Clark \u003cjames.clark@linaro.org\u003e\nLink: https://lore.kernel.org/r/20250606052602.3387225-1-anshuman.khandual@arm.com\n[ Mark: remove unecessary comment and brackets ]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2b3a659fad552119ff9e7527d4ebe8c13e3ea896",
      "old_mode": 33188,
      "old_path": "arch/aarch64/include/asm/cpu.h",
      "new_id": "ac50474b8ab2d5b0e6ddefe46b04449dc090700b",
      "new_mode": 33188,
      "new_path": "arch/aarch64/include/asm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "e1640a91f310b58f65ba51eb62b59c5fb53538cc",
      "old_mode": 33188,
      "old_path": "arch/aarch64/init.c",
      "new_id": "cb24f4e69cf7a613b957fbfaac1665617eb9a9bc",
      "new_mode": 33188,
      "new_path": "arch/aarch64/init.c"
    }
  ]
}