)]}' { "log": [ { "commit": "b621b157b42f1fe398520cf499db88aa654c78e2", "tree": "fd0737494e69c188dd2b662b50856a772a105895", "parents": [ "785302c1f7b9eceab3b72a8cb3d79eaf526fd2e3" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Fri Jun 06 10:56:02 2025 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jun 10 18:14:43 2025 +0100" }, "message": "aarch64: Enable access into FEAT_SPE_FDS register from EL2 and below\n\nFEAT_SPE_FDS adds system register PMSDSFR_EL1. But accessing that system\nregister from EL2 and below exception levels, will trap into EL3 unless\nMDCR_EL3.EnPMS3 is set.\n\nEnable access to FEAT_SPE_FDS registers when they are implemented.\n\nCc: James Clark \u003cjames.clark@linaro.org\u003e\nCc: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nReviewed-by: James Clark \u003cjames.clark@linaro.org\u003e\nLink: https://lore.kernel.org/r/20250606052602.3387225-1-anshuman.khandual@arm.com\n[ Mark: remove unecessary comment and brackets ]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "785302c1f7b9eceab3b72a8cb3d79eaf526fd2e3", "tree": "1c73c807a5e339db9a75739da1b4a131caede8e0", "parents": [ "7f5a545526750bd8f114a0194ef0fea9d83406fd" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Sun May 11 10:52:11 2025 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed May 14 07:03:59 2025 +0100" }, "message": "aarch64: Enable use of ZT0\n\nFEAT_SME2 adds the ZT0 register. Accesses to ZT0 trap to EL3 unless\nSMCR_EL3.EZT0 is set, and so boot-wrapper support is necessary.\n\nSupport for FEAT_SME2 was added to Linux in v6.3 without any\nboot-wrapper support. Consequently when SME2 is enabled in a model, any\nattempt to access ZT0 (whether in userspace, kernel, or hypervisor) will\nresult in a hang. Linux will (only) access ZT0 during a context switch\nwhen PSTATE.ZA\u003d\u003d1, and so this hang is seen long after boot, when\napplications first set PSTATE.ZA.\n\nAdd boot-wrapper support for ZT0, as described in the latest ARM ARM\n(ARM DDI 0487 L.a), which can be found at:\n\n https://developer.arm.com/documentation/ddi0487/la/?lang\u003den\n\nAll we need to do at EL3 is set SMCR_EL3.EZT0; it\u0027s up to lower ELs to\nconfigure their SMCR_ELx register appropriately.\n\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\nLink: https://lore.kernel.org/r/20250511095211.1638852-4-mark.rutland@arm.com\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "7f5a545526750bd8f114a0194ef0fea9d83406fd", "tree": "39879a78ef608bc0dc37822fe30411609baa1c15", "parents": [ "0f3a153a942be8511fe528e68c9c7145d854d125" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Sun May 11 10:52:10 2025 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed May 14 07:03:59 2025 +0100" }, "message": "aarch64: Enable use of FPMR\n\nFEAT_FPMR adds the FPMR register. Acceses to FPMR (whether direct or\nindirect) trap to EL3 unless SCR_EL3.EnFPM is set, and so boot-wrapper\nsupport is necessary.\n\nSupport for FEAT_FPMR was added to Linux in v6.8 without any\nboot-wrapper support. Consequently when FPMR is enabled in a model, the\nkernel will hang when attempting to write to the FPMR (e.g. when\nentering userspace for the first time).\n\nAdd boot-wrapper support for FEAT_FPMR, as described in the latest ARM\nARM (ARM DDI 0487 L.a), which can be found at:\n\n https://developer.arm.com/documentation/ddi0487/la/?lang\u003den\n\nThe ID_AA64PFR2_EL1 ID register has existed as reserved RES0 space since\nARMv8.0 but only recently gained a name, and so older assemblers may not\nbe able to encode ID_AA64PFR2_EL1 directly. Thus we need an explicit\ndefinition of the sysreg encoding to support these assemblers.\n\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\nLink: https://lore.kernel.org/r/20250511095211.1638852-3-mark.rutland@arm.com\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "0f3a153a942be8511fe528e68c9c7145d854d125", "tree": "25155df3b84590cbc5fb3f72f33ed100b91e3521", "parents": [ "0e784924ad406a300069f8aa93dac350056c475a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Sun May 11 10:52:09 2025 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed May 14 07:03:59 2025 +0100" }, "message": "aarch64: shuffle ID_AA64PFR{0,1}_EL1 definitions\n\nUsually the ID register definitions are sorted alphanumerically, but for\nhistorical reasons the ID_AA64PFR0_* definitions are placed before the\nID_AA64PFR1_* definitions. Reorder these for consistency.\n\nThere should be no functional change as a result of this patch.\n\nLink: https://lore.kernel.org/r/20250511095211.1638852-2-mark.rutland@arm.com\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "0e784924ad406a300069f8aa93dac350056c475a", "tree": "00055d768db62b2a8d3aca7801d190a9f137301a", "parents": [ "1571345a9968bce9a074f7370ff15a985e300ffc" ], "author": { "name": "Dave Martin", "email": "Dave.Martin@arm.com", "time": "Mon May 12 16:09:44 2025 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon May 12 16:45:45 2025 +0100" }, "message": "Makefile: Ensure initrd parameters in /chosen are up-to-date\n\nThe initrd parameters in the FDT /chosen node are fixed when the device\ntree blob is generated, so it is important to regenerate the device\ntree if the initrd image has been updated.\n\nCurrently this does not happen, so the parameters can be stale.\nIn particular, if the initrd image is bigger than it was when the\ndevice tree was first generated then the value of the linux,initrd-end\nparameter is too small, leading to truncation of the initrd image on\nboot even though the whole image is present in linux-system.axf.\n\nMake $(FILESYSTEM) a dependency of fdt.dtb so that the parameters are\nrefreshed properly based on the current initrd image (if any).\n\nWithout --with-initrd, FILESYSTEM is the empty string and the\ndependency evaporates, which is just fine.\n\nSigned-off-by: Dave Martin \u003cDave.Martin@arm.com\u003e\nLink: https://lore.kernel.org/r/20250512150944.38322-1-Dave.Martin@arm.com\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "1571345a9968bce9a074f7370ff15a985e300ffc", "tree": "a933a41c3c089818db9e1b93b56efa50c39cc02d", "parents": [ "e1b9137eec2f07329a57d8868dc4c26802abf29f" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Thu Feb 27 09:46:03 2025 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Apr 04 11:27:55 2025 +0100" }, "message": "aarch64: Enable access into FEAT_PMUv3p9 registers from EL2 and below\n\nFEAT_PMUv3p9 adds system register PMUACR_EL1 and similarly FEAT_PMUv3_ICNTR\nadds system registers PMICFILTR_EL0 and PMICNTR_EL0. But access into these\nsystem registers from EL2 and below exception levels, will trap into EL3\nunless MDCR_EL3.EnPM2 is set.\n\nEnable access to FEAT_PMUv3p9 registers when they are implemented.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nLink: https://lore.kernel.org/r/20250227041603.2029058-1-anshuman.khandual@arm.com\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "e1b9137eec2f07329a57d8868dc4c26802abf29f", "tree": "cb2c8c1aa367c33f3f5cada806564941a2576126", "parents": [ "ac6742520ded1da30d500f74e8affe86e27cabd5" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Tue Jul 30 11:16:43 2024 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Feb 24 11:51:54 2025 +0000" }, "message": "aarch64: Enable access into FEAT_FGT2 registers from EL2 and below\n\nFEAT_FGT2 adds system registers HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2,\nHFGRTR2_EL2 and HFGWTR2_EL2. But access into these system registers from\nEL2 and below exception levels, will trap into EL3 unless SCR_EL3.FGTEN2\nis set.\n\nEnable access to FEAT_FGT2 registers when they are implemented. Given that\nthese new FEAT_FGT2 trap registers have fields that reset to UNKNOWN values\nwhen resets are taken to EL3, this initialises all registers as cleared.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20240730054643.157295-1-anshuman.khandual@arm.com\n" }, { "commit": "ac6742520ded1da30d500f74e8affe86e27cabd5", "tree": "a09eb7793a116e66946c304fcbbcd0ae51550cd3", "parents": [ "ba899d1d72279316d1487fef97317a86aa1787bc" ], "author": { "name": "Luca Fancellu", "email": "luca.fancellu@arm.com", "time": "Wed Nov 27 10:23:00 2024 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Dec 02 09:45:32 2024 +0000" }, "message": "aarch64: Start Xen on Armv8-R at EL2\n\nWhen bootwrapper is compiled with Xen support and it is started\nat EL2 on Armv8-R AArch64, keep the current EL and jump to the\nXen image using the SPSR_KERNEL as spsr_el2 value.\n\nThe only available boot method on Armv8-R AArch64 when starting\nXen is spin table at the moment, reflect this in the build\nconfiguration.\n\nSigned-off-by: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n[Mark: tweak configure.ac error message]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20241127102300.2822848-1-luca.fancellu@arm.com\n" }, { "commit": "ba899d1d72279316d1487fef97317a86aa1787bc", "tree": "79fd138ee3e4dc6a4fcf8b6e794a40b55601ba94", "parents": [ "476a0b6451d776181f954f9c896a2962c7436c44" ], "author": { "name": "Luca Fancellu", "email": "luca.fancellu@arm.com", "time": "Thu Oct 17 10:55:19 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Nov 26 11:50:01 2024 +0000" }, "message": "aarch64: Implement PSCI for Armv8-R\n\nArmv8-R doesn\u0027t have EL3, so the PSCI vector needs to be\ninstalled in VBAR_EL2 and the conduit needs to be \u0027hvc\u0027\ninstead of \u0027smc\u0027.\n\nImplement the modifications needed when --with-bw-arch is\n\u0027aarch64-r\u0027.\n\nSigned-off-by: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20241017095520.939464-4-luca.fancellu@arm.com\n" }, { "commit": "476a0b6451d776181f954f9c896a2962c7436c44", "tree": "6343466cb5f66484575f3da9609a0a6398e93abe", "parents": [ "0f00cf4cb8b2bd88fc6f587e67fed6ba02bb2570" ], "author": { "name": "Luca Fancellu", "email": "luca.fancellu@arm.com", "time": "Thu Oct 17 10:55:18 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Nov 26 11:43:04 2024 +0000" }, "message": "aarch64: Enable Armv8-R EL2 boot\n\nWhen booting on Armv8-R, EL3 is not implemented and the Linux\nkernel needs to be booted in EL1, so initialise EL2 and start\nthe kernel in the expected exception level.\n\nTo do so, introduce the \u0027aarch64-r\u0027 argument for the\n--with-bw-arch parameter.\n\nPSCI is not yet implemented for aarch64-r.\n\nSigned-off-by: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20241017095520.939464-3-luca.fancellu@arm.com\n" }, { "commit": "0f00cf4cb8b2bd88fc6f587e67fed6ba02bb2570", "tree": "823f2b03bd85840b2af4ffb0bef9c64d1e652874", "parents": [ "aafb5958eb9df8c39872c24d4f48000ea179fb35" ], "author": { "name": "Luca Fancellu", "email": "luca.fancellu@arm.com", "time": "Thu Oct 17 10:55:17 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Nov 26 11:43:04 2024 +0000" }, "message": "Introduce --with-bw-arch for boot-wrapper compile arch\n\nIntroduce a new autoconf parameter --with-bw-arch that takes\n\u0027aarch64-a\u0027 and \u0027aarch32-a\u0027 as compile architecture, the former\nis selected by default when the parameter is not passed.\n\nThis new parameter superseed --enable-aarch32-bw, its functionality\nis now implemented by --with-bw-arch\u003daarch32-a.\n\nSigned-off-by: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20241017095520.939464-2-luca.fancellu@arm.com\n" }, { "commit": "aafb5958eb9df8c39872c24d4f48000ea179fb35", "tree": "700fc0e0281227e831f710f5efdf84e8d3bb389f", "parents": [ "d62de19c866141cb450576040439de233438fb60" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 12:30:49 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 11:54:14 2024 +0100" }, "message": "Boot CPUs sequentially\n\nCurrently the boot-wrapper initializes all CPUs in parallel. This means\nthat we cannot log errors as they happen, as this would mean multiple\nCPUs concurrently writing to the UART, producing garbled output. To\nproduce meaningful output we have to special-case errors on the boot CPU\nand hope CPUs have been configured consistently.\n\nTo make it easier to handle errors, boot CPUs sequentially so that errors\ncan be logged as they happen. With this change it\u0027s pretty clear that\nthe cpu_init_bootmethod() abstraction isn\u0027t helpful, and so this is\nremoved with cpu_init_arch() directly initializing PSCI where necessary.\n\nWhen things go well this looks like:\n\n| Boot-wrapper v0.2\n| Entered at EL3\n| Memory layout:\n| [0000000080000000..0000000080001f90] \u003d\u003e boot-wrapper\n| [000000008000fff8..0000000080010000] \u003d\u003e mbox\n| [0000000080200000..0000000082cbaa00] \u003d\u003e kernel\n| [0000000088000000..0000000088002df1] \u003d\u003e dtb\n| CPU0: (MPIDR 0000000000000000) initializing...\n| CPU1: (MPIDR 0000000000000100) initializing...\n| CPU2: (MPIDR 0000000000000200) initializing...\n| CPU3: (MPIDR 0000000000000300) initializing...\n| CPU4: (MPIDR 0000000000010000) initializing...\n| CPU5: (MPIDR 0000000000010100) initializing...\n| CPU6: (MPIDR 0000000000010200) initializing...\n| CPU7: (MPIDR 0000000000010300) initializing...\n| All CPUs initialized. Entering kernel...\n|\n| [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd0f0]\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "d62de19c866141cb450576040439de233438fb60", "tree": "e1478f70926395e34986834ddd1f3e204e6103e6", "parents": [ "1ab497ed6c38bc533852b1bd46c807a38e32517f" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 12:27:13 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 11:53:51 2024 +0100" }, "message": "Add printing functions\n\nIn subsequent patches we\u0027ll want to log messages from specific CPUs. Add\nhelpers to make this simpler.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "1ab497ed6c38bc533852b1bd46c807a38e32517f", "tree": "73d07df8b4863239ebc3d11e7abe3ba74fbf779f", "parents": [ "1e576e54d0a4334b82d4704a4c34e4e33bafd686" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 19 17:33:14 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 11:53:51 2024 +0100" }, "message": "Simplify spin logic\n\nThe logic for initial boot is more complicated than it needs to be,\nwith both first_spin() having a special case for CPU0 that requires an\nadditional argument to be passed to spin().\n\nSimplify this by moving the special-case logic for CPU0 into\nfirst_spin(). This removes the need to provide a dummy mailbox for CPU0\nto spin on, simplfiies callers of first_spin() and spin(), which no\nlonger need to pass a dummy mailbox or \u0027is_entry\u0027 for CPU0.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "1e576e54d0a4334b82d4704a4c34e4e33bafd686", "tree": "7794066295f5bfc24dd34e0bf9142cabcd5ee0e7", "parents": [ "19ffbec99cf531a7b05ff75720fd9b2f0b5f3334" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 10:51:17 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 11:53:51 2024 +0100" }, "message": "Unify assembly setup paths\n\nThe early assembly paths for EL3/Secure-PL1 and EL2/Hyp are almost\nidentical aside from the EL3/Secure-PL1 paths calling gic_secure_init().\n\nSimplify the early assembly paths by conditionally calling\ngic_secure_init() from cpu_init_arch(), allowing the EL3/Secure-PL1 and\nEL2/Hyp paths to be unified.\n\nIn order to call gic_secure_init() from C code we need to expose a\nprototype for gic_secure_init(), requiring a new \u003cgic.h\u003e header. For\nclarity the existing \u003casm/gic-v3.h\u003e headers are renamed to \u003casm/gic.h\u003e\nand are included through the common header.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "19ffbec99cf531a7b05ff75720fd9b2f0b5f3334", "tree": "2bdaaf6d5d3ef94fb6d3208d08a0924f3d0af31a", "parents": [ "e8e6f797bafadfa16f70ab00e36aa5a4a140c53f" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 10:28:45 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 11:53:46 2024 +0100" }, "message": "aarch32: Always enter kernel via exception return\n\nWhen the boot-wrapper is entered at Secure PL1 it will enter the kernel\nvia an exception return, and when entered at Hyp it will branch to the\nkernel directly. This is an artifact of the way the boot-wrapper was\noriginally written in assembly, and it would be preferable to always\nenter the kernel via an exception return so that PSTATE is always\ninitialized to a known-good value.\n\nRework jump_kernel() to always enter the kernel via an exception return,\nmatching the style of the AArch64 version of jump_kernel()\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "e8e6f797bafadfa16f70ab00e36aa5a4a140c53f", "tree": "59f2164c3e84547a623c5ce624024d5470941c0c", "parents": [ "8745a2cd8e0af71bb2982c4dcb21859ebfb31020" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 09:23:48 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 20 12:17:57 2024 +0100" }, "message": "aarch32: Implement cpu_init_arch()\n\nWhen the boot-wrapper is entered at EL2/Hyp it does not initialise\nCNTFRQ, and in future it may need to initialize other CPU state\nregardless of the exeption level it was entered at.\n\nUse a common cpu_init_arch() function to initialize CPU state regardless\nof the exception level the boot-wrapper was entered at. For clarity\ncpu_init_secure_pl1() is renamed to cpu_init_monitor(), which better\nmatches PSR_MON and will allow for the addition of cppu_init_hyp() and\ncpu_init_svc() in future.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "8745a2cd8e0af71bb2982c4dcb21859ebfb31020", "tree": "9091e431e1ddfa00d7ad37f799c1a6b722ce0e00", "parents": [ "77c3316737fcb5240d37d6eca2386584688c6d3b" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 24 10:00:45 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 20 12:04:08 2024 +0100" }, "message": "aarch32: Refactor inital entry\n\nFor historical reasons the early AArch32 code is structured differently\nfrom the early AArch64 code, with some common code (including stack\nsetup) performed before we identify the mode we were entered in.\n\nAlign the structure of the early AArch32 code with that of the early\nAArch64 code. This will make subsequent refactoring easier.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "77c3316737fcb5240d37d6eca2386584688c6d3b", "tree": "93c25218bdea08d7bd36191e3e60c7300892b242", "parents": [ "308d25f908a86f698cc40994a907fdd7e1f1c6f8" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 23 15:04:26 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 20 12:04:05 2024 +0100" }, "message": "aarch64: Always enter kernel via exception return\n\nWhen the boot-wrapper is entered at EL3 it will enter the kernel via\nERET, and when entered at EL2 it will branch to the kernel directly.\nThis is an artifact of the way the boot-wrapper was originally written\nin assembly, and it would be preferable to always enter the kernel via\nERET so that PSTATE is always initialized to a known-good value.\n\nRework jump_kernel() to always enter the kernel via ERET.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "308d25f908a86f698cc40994a907fdd7e1f1c6f8", "tree": "6c613ff252f5e3c88b033dba3ff87e446cd4545c", "parents": [ "4dcb17f55300db48388b15d56a7b207df5a4a8e7" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 23 14:38:23 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 20 12:03:29 2024 +0100" }, "message": "aarch64: Implement cpu_init_arch()\n\nWhen the boot-wrapper is entered at EL2 it does not initialise\nCNTFRQ_EL0, and in future it may need to initialize other CPU state\nregardless of the exeption level it was entered at.\n\nUse a common cpu_init_arch() function to initialize CPU state regardless\nof the exception level the boot-wrapper was entered at.\n\nThis change means that the boot-wrapper can only be used when enetered\nat the highest implemented exception level, as accesses to CNTFRQ_EL0\nwill be UNDEFINED at lower exception levels. However, the boot-wrapper\nonly supports being booted at the highest implemented exception level,\nas the comment at the top of boot.S describes:\n\n| The boot-wrapper must be entered from the reset vector at the\n| highest implemented exception level.\n\n... so this should not adversely affect any supported configuration.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "4dcb17f55300db48388b15d56a7b207df5a4a8e7", "tree": "d2ff3b5e066040e24bcefcf3a4705d8ef07e23ef", "parents": [ "400f0a86dcc85f3e55882ef1451778a3cfba59ca" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 23 15:01:33 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 20 12:03:27 2024 +0100" }, "message": "aarch64: Remove redundant EL1 entry logic\n\nFor historical reasons the boot-wrapper has code to handle being entered\nat Non-secure EL1, but currently this is unsupported and cannot be used\nto boot a kernel as jump_kernel() unconditionally writes to SCTLR_EL2,\nwhich will UNDEF.\n\nRemove the logic for handling Non-secure EL1.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\n" }, { "commit": "400f0a86dcc85f3e55882ef1451778a3cfba59ca", "tree": "8a2fae9bfd04843137f8ab7772ac76087ea137d7", "parents": [ "1fea854771f9aee405c4ae204c0e0f912318da6f" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 02 12:17:29 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Sat Aug 03 11:40:37 2024 +0100" }, "message": "Revert \"configure: allow the use of bare-metal toolchains\"\n\nWhile well-intentioned, the CFLAGS change to support bare metal\ntoolchains introduced at least two problems:\n\n(1) It broke building on an AArch64 host when *not* passing \u0027--host\u003d[...]\u0027, as\n the bare-metal object files built during the configure step can\u0027t be\n executed on the host:\n\n | [mark@gravadlaks:~/src/boot-wrapper-aarch64]% ./configure --enable-gicv3 --with-kernel-dir\u003d../linux-kvm\n | checking for a BSD-compatible install... /usr/bin/install -c\n | checking whether build environment is sane... yes\n | checking for a race-free mkdir -p... /usr/bin/mkdir -p\n | checking for gawk... no\n | checking for mawk... mawk\n | checking whether make sets $(MAKE)... yes\n | checking whether make supports nested variables... yes\n | checking whether DTB file exists... yes\n | checking whether kernel image exists... yes\n | checking for gcc... gcc\n | checking whether the C compiler works... yes\n | checking for C compiler default output file name... a.out\n | checking for suffix of executables...\n | checking whether we are cross compiling... configure: error: in `/home/mark/src/boot-wrapper-aarch64\u0027:\n | configure: error: cannot run C compiled programs.\n | If you meant to cross compile, use `--host\u0027.\n | See `config.log\u0027 for more details\n\n(2) It removed the implicit default CFLAGS used by autoconf (\u0027-g -O2\u0027),\n and consequently the boot-wrapper was compiled at a lower\n optimization level. This caused functions to use more stack space,\n and for CPUs to clobber other CPUs\u0027 stacks during initialization,\n leading to various potential issues including misconfiguration of\n the system.\n\nWe can solve (2) by adding \u0027-O2\u0027 manually and/or increasing STACK_SIZE\nfrom 256 bytes, but (1) is much more painful to solve as we end up\nhaving to work around the core design of autoconf.\n\nFor now, revert the problematic commit.\n\nThis reverts commit 1fea854771f9aee405c4ae204c0e0f912318da6f.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReported-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nCc: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20240802111729.2154293-1-mark.rutland@arm.com\n" }, { "commit": "1fea854771f9aee405c4ae204c0e0f912318da6f", "tree": "67142a21f6886569164d132d837cf6efc3a99844", "parents": [ "784feb9b07530d61302662fdde53ab242164e5f7" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 15:31:16 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 02 11:07:12 2024 +0100" }, "message": "configure: allow the use of bare-metal toolchains\n\nCurrently it is not possible to build the boot-wrapper with a bare-metal\ntoolchain, as the configure script tries to build a hosted object. For\nexample, trying to build with the bare-metal aarch64-linux GCC 13.2.0\ntoolchain from kernel.org fails with:\n\n| [mark@lakrids:~/src/boot-wrapper-aarch64]% usekorg 13.2.0 ./configure --enable-gicv3 --host\u003daarch64-linux --with-kernel-dir\u003d../linux --with-cmdline\u003d\"console\u003dttyAMA0 earlycon\u003dpl011,0x1c090000 root\u003d/dev/vda kvm_arm.mode\u003dvhe\"\n| checking for a BSD-compatible install... /usr/bin/install -c\n| checking whether build environment is sane... yes\n| checking for aarch64-linux-strip... aarch64-linux-strip\n| checking for a thread-safe mkdir -p... /usr/bin/mkdir -p\n| checking for gawk... gawk\n| checking whether make sets $(MAKE)... yes\n| checking whether make supports nested variables... yes\n| checking whether DTB file exists... yes\n| checking whether kernel image exists... yes\n| checking for aarch64-linux-gcc... aarch64-linux-gcc\n| checking whether the C compiler works... no\n| configure: error: in `/home/mark/src/boot-wrapper-aarch64\u0027:\n| configure: error: C compiler cannot create executables\n| See `config.log\u0027 for more details\n\nThis behaviour was an unintentional side-effect of moving to autotools\nin commit:\n\n bae4ae6a834cd15b (\"Add autotools configuration.\")\n\n... as the default CFLAGS end up trying to build a hosted object.\n\nPass the necessary CFLAGS to build a bare-metal object. matching what we\ndo in Makefile.am, so that the configure script doesn\u0027t reject\nbare-metal toolchains.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nCc: Marc Zyngier \u003cmaz@kernel.org\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20240729143116.1804615-4-mark.rutland@arm.com\n" }, { "commit": "784feb9b07530d61302662fdde53ab242164e5f7", "tree": "8a2fae9bfd04843137f8ab7772ac76087ea137d7", "parents": [ "e1d7651f3c2f78fe86da080d5096b459b41f775a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 15:31:15 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 02 11:07:12 2024 +0100" }, "message": "Makefile: suppress RWX segment warnings\n\nContemporary versions of GNU LD warn about segments with RWX\npermissions, which can occur when building the boot-wrapper, e.g.\n\n| aarch64-linux-ld: warning: linux-system.axf has a LOAD segment with RWX permissions\n\nThis is due to sections with RW- and R-X being adjacent, and getting combined\ninto a single segment with RWX permissions:\n\n| [mark@lakrids:~/src/boot-wrapper-aarch64]% readelf -l linux-system.axf\n|\n| Elf file type is EXEC (Executable file)\n| Entry point 0x80000000\n| There are 4 program headers, starting at offset 64\n|\n| Program Headers:\n| Type Offset VirtAddr PhysAddr\n| FileSiz MemSiz Flags Align\n| LOAD 0x0000000000010000 0x0000000080000000 0x0000000080000000\n| 0x0000000000010000 0x0000000000010000 RWE 0x10000\n| LOAD 0x0000000000020000 0x0000000080200000 0x0000000080200000\n| 0x000000000331b200 0x000000000331b200 RW 0x10000\n| LOAD 0x0000000003340000 0x0000000088000000 0x0000000088000000\n| 0x0000000000002e05 0x0000000000002e05 RW 0x10000\n| GNU_STACK 0x0000000000000000 0x0000000000000000 0x0000000000000000\n| 0x0000000000000000 0x0000000000000000 RW 0x10\n|\n| Section to Segment mapping:\n| Segment Sections...\n| 00 .boot .mbox\n| 01 .kernel\n| 02 .dtb\n| 03\n\nSince the bootwrapper runs with the MMU off, the RWX permissions aren\u0027t\na problem, and the simplest solution is to suppress the warning with the\n\u0027--no-warn-rwx-segments\u0027 option to LD.\n\nAdd the necessary logic to suprress the warning when supported by LD.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nCc: Marc Zyngier \u003cmaz@kernel.org\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20240729143116.1804615-3-mark.rutland@arm.com\n" }, { "commit": "e1d7651f3c2f78fe86da080d5096b459b41f775a", "tree": "d6543a1a2478820ae6663afa0214acd111d3ba8f", "parents": [ "cd7fe8a88e829055360d2dbe36e0912b9db33d3a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 15:31:14 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 02 11:07:12 2024 +0100" }, "message": "Makefile: rework test-dtc-option\n\nCurrently we have the test-dtc-option helepr to check whether dtc\nsupports an option. In subsequent patches we\u0027ll want similar for ld, and\nit seems likely that we\u0027ll want this for other commands in future.\n\nThis patch adds a new test-cmd helper that can be used to check whether\na command succeeds (based on its return value), and can be used to\nchoose between a value if the comand succeeds and a value if the command\nfails.\n\nThe existing test-dtc-option helper is reworked to use test-cmd. The\nhelpers are added near the start of the file so that they\u0027ll be defined\nprior to usage whetever they\u0027re used within the file. This is purely for\nhuman comprehension as Make itself does not care about their location\nwithin the Makefile.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Akos Denke \u003cakos.denke@arm.com\u003e\nCc: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nCc: Marc Zyngier \u003cmaz@kernel.org\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20240729143116.1804615-2-mark.rutland@arm.com\n" }, { "commit": "cd7fe8a88e829055360d2dbe36e0912b9db33d3a", "tree": "14acdc05ead037f10c3c14889cce4b170496627b", "parents": [ "1ac2031460031641929f247a743f3884deb05157" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Mon Jul 29 10:06:06 2024 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 13:49:18 2024 +0100" }, "message": "aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below\n\nFEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system\nregisters from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set.\n\nEnable access to RCW[S]MASK_EL1 registers when they are implemented.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20240729043606.871451-4-anshuman.khandual@arm.com\n" }, { "commit": "1ac2031460031641929f247a743f3884deb05157", "tree": "d2a13caad60b0f8902229286e3bcd19e3b487a9c", "parents": [ "b13b3bdcb2a1d17c9e286639eb0489ee7fe62c35" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Mon Jul 29 10:06:05 2024 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 13:49:18 2024 +0100" }, "message": "aarch64: Enable access into 128 bit system registers from EL2 and below\n\nFEAT_D128 adds 128 bit system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1,\nTTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and\nRCWSMASK_EL1. But access into these register from EL2 and below trap to EL3\nunless SCR_EL3.D128En is set.\n\nEnable access to 128 bit registers when they are implemented.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20240729043606.871451-3-anshuman.khandual@arm.com\n" }, { "commit": "b13b3bdcb2a1d17c9e286639eb0489ee7fe62c35", "tree": "a6c4041a53dc082b8faaf2b3f488cb49904a42a9", "parents": [ "61b84b4a1c02b78277b3b9fa1ca00f82b1705beb" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Mon Jul 29 10:06:04 2024 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 29 13:49:18 2024 +0100" }, "message": "aarch64: Enable access into SCTLR2_ELx registers from EL2 and below\n\nFEAT_SCTLR2 adds SCTLR2_EL1 and SCTLR2_EL2 system registers. But access\ninto these register from EL2 and below exception levels, will trap into EL3\nunless SCR_EL3.SCTLR2En is set.\n\nEnable access to SCTLR2_ELx registers when they are implemented. Given that\nSCTLR2_ELx registers reset to UNKNOWN values - when the highest implemented\nexception level is not ELx, this resets SCTLR2_ELx registers. Otherwise any\nkernel which is not aware of these SCTLR2_ELx registers, will be subject to\narbitrary behaviour as a result of the SCTLR2_ELx bits which it will not\nhave configured.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20240729043606.871451-2-anshuman.khandual@arm.com\n" }, { "commit": "61b84b4a1c02b78277b3b9fa1ca00f82b1705beb", "tree": "41b1a5b5c66b5a78c3d00d02366cf43f3453b5eb", "parents": [ "3bac221638c41d52e818ffe36387cf8079181ec1" ], "author": { "name": "Luca Fancellu", "email": "luca.fancellu@arm.com", "time": "Tue Jul 16 15:29:03 2024 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 19 11:01:30 2024 +0100" }, "message": "aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET\n\nFrom the specification SCTLR_EL2.TSCXT is RES1 only \"When\nFEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not\nimplemented, HCR_EL2.E2H \u003d\u003d 1 and HCR_EL2.TGE \u003d\u003d 1\", so\ngiven that HCR_EL2.E2H is set by bootwrapper before to a\nvalue of zero, the condition above can\u0027t happen and from\nthe specification the bit is RES0.\n\nFix the macro removing the bit.\n\nSigned-off-by: Luca Fancellu \u003cluca.fancellu@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "3bac221638c41d52e818ffe36387cf8079181ec1", "tree": "8472559f107b7ca6ea0a371dfce06b80522784cc", "parents": [ "5e3760073454c72f3458805a1b7a89ecf80353cb" ], "author": { "name": "Akos Denke", "email": "akos.denke@arm.com", "time": "Thu May 23 13:49:31 2024 +0200" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 19 10:36:00 2024 +0100" }, "message": "configure: make --with-kernel-dir optional\n\nCurrently it is mandatory to specify the kernel directory via\n--with-kernel-dir, and this is used to generate default paths for the\nkernel image, dtb, and dtc.\n\nAll of these paths can all be provided by the user, e.g. the kernel\nimage path can be provided by --with-kernel-image, and an alternative\ndtc can be added to $PATH. When all of these are provided by the user,\nthere\u0027s no real need for the kernel directory.\n\nDrop the requirement for --with-kernel-dir when other paths are provided\nexplicitly. This makes it easier to use the boot-wrapper with prebuilt\nkernels, where we do not control the directory structure of the kernel\nartifacts.\n\nSigned-off-by: Akos Denke \u003cakos.denke@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n[Mark: simplify commit message, rework option parsing, always log kernel dir]\nLink: https://lore.kernel.org/r/20240523114931.2093222-1-akos.denke@arm.com\n" }, { "commit": "5e3760073454c72f3458805a1b7a89ecf80353cb", "tree": "5439d82c722be56c0de0b200e81c61b70d1506c7", "parents": [ "44e25f43712597a75f1a5e547c66881b3750e0cf" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Thu Apr 04 13:07:25 2024 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 18 11:19:50 2024 +0100" }, "message": "aarch64: Enable access to MDSELR_EL1 from EL2 and below\n\nFEAT_Debugv8p9 adds a new MDSELR_EL1 register to select between banks of\nbreakpoints and watchpoints. Accesses to MDSELR_EL1 from EL2 and below trap to\nEL3 unless MDCR_EL3.EBWE is set.\n\nEnable access to MDSELR_EL1 when it is implemented.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "44e25f43712597a75f1a5e547c66881b3750e0cf", "tree": "2f6e5919357e6947c8923a29d16b785ed9239209", "parents": [ "226fddeaaa1295688ddbad563b67b1c90113efeb" ], "author": { "name": "Joey Gouly", "email": "joey.gouly@arm.com", "time": "Fri Jun 16 17:00:36 2023 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jun 19 09:31:45 2023 +0100" }, "message": "aarch64: enable Permission Indirection Extension\n\nAllow lower ELs to access the registers associated with the Permission\nIndirection Extension.\n\nSigned-off-by: Joey Gouly \u003cjoey.gouly@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "226fddeaaa1295688ddbad563b67b1c90113efeb", "tree": "e87ef8aa713643524b21a25d568e46cea4e78297", "parents": [ "9f26a1c1f27bd6b5b66c265114848007fc22e4aa" ], "author": { "name": "Joey Gouly", "email": "joey.gouly@arm.com", "time": "Fri Jun 16 17:00:35 2023 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jun 19 09:31:45 2023 +0100" }, "message": "aarch64: enable access to TCR2_ELx\n\nAllow access the TCR2_ELx register which provides extended translation\ncontrols similar to TCR_ELx.\n\nInitialise these registers to a value of 0.\n\nSigned-off-by: Joey Gouly \u003cjoey.gouly@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "9f26a1c1f27bd6b5b66c265114848007fc22e4aa", "tree": "ae796ae053560dc9b053cefbf7f5d4d041956b13", "parents": [ "229002a9e6a3245315e3a2fedb8b0df0c904a0c6" ], "author": { "name": "Kevin Brodsky", "email": "kevin.brodsky@arm.com", "time": "Mon Jan 02 13:24:46 2023 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jan 30 14:40:51 2023 +0000" }, "message": "model.lds.S: Quote file paths\n\nInserting arbitrary paths in a linker script verbatim can be\nproblematic, even if they don\u0027t contain whitespaces, as ld has a\nspecial interpretation for certain special characters (such as @).\n\nFix this by quoting all user-provided paths in model.lds.S using the\npreprocessor.\n\nSigned-off-by: Kevin Brodsky \u003ckevin.brodsky@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "229002a9e6a3245315e3a2fedb8b0df0c904a0c6", "tree": "73ab2cacc6248ef0781825377f6f7ae2586bfedc", "parents": [ "c46a09cf1d8e4e34b64f06132acf2effbc85e48d" ], "author": { "name": "Peter Hoyes", "email": "Peter.Hoyes@arm.com", "time": "Tue Feb 15 11:54:18 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jan 30 14:20:59 2023 +0000" }, "message": "Makefile: Change COUNTER_FREQ to 100 MHz\n\nOlder Arm Fast Models (AEM \u003c RevC) had a base frequency of 24 MHz. but\nthe RevC base models use 100 MHz. There is not a robust method of\ndetermining the configured base frequency at runtime, so update\nCOUNTER_FREQ to be 100 MHz.\n\nSigned-off-by: Peter Hoyes \u003cPeter.Hoyes@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "c46a09cf1d8e4e34b64f06132acf2effbc85e48d", "tree": "e47d9dc8ea0ddfff3a027e4fa22ff098079c5473", "parents": [ "5aeb34ee72c055d886034c8d0b54c29bd49ad9fb" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 04 15:51:52 2022 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Oct 04 16:15:24 2022 +0100" }, "message": "sme: Fix sign-extension bug in SMCR_EL3 write\n\nTo enable the full AArch64 ISA support in streaming SVE mode, we need to\nset bit 31 in the SMCR_EL3 system register. However ORing (1 \u003c\u003c 31) into\nan unsigned long variable will lead to all upper 32 bits becoming 1,\nwhich is not what we want. We are just saved by those bits being RES0,\nat least for now.\n\nExplicitly use an unsigned base for the shift, to avoid the sign\nextension.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n[Mark: use \u0027BIT(31)\u0027 rather than \u0027(1U \u003c\u003c 31)\u0027]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20221004145152.3020464-1-andre.przywara@arm.com/\n" }, { "commit": "5aeb34ee72c055d886034c8d0b54c29bd49ad9fb", "tree": "06434f66fc4671c292f366769af25d0acdc9a286", "parents": [ "80c2c9bf88ae51c346dac958308782f80be84339" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue May 17 14:43:05 2022 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Oct 04 16:03:57 2022 +0100" }, "message": "fix array boundary check in find_logical_id\n\nWhen we are trying to find the array index for a given MPIDR, we check\nthat we don\u0027t overrun the array boundary, by comparing against NR_CPUS.\nHowever the resulting conditional branch should also fire when we reach\nthe exact number of elements, since it\u0027s all 0 based.\n\nChange the comparison to be \u0027\u003e\u003d\u0027 instead of just \u0027\u003e\u0027, to only allow\narray indicies 0 .. (NR_CPUS - 1).\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "80c2c9bf88ae51c346dac958308782f80be84339", "tree": "0af59bbecafbfd17a9c0ae5606fd38458a818b62", "parents": [ "6a0fc40035f9bb581054eb26fbac3c659cfa99b2" ], "author": { "name": "Kristina Martsenko", "email": "kristina.martsenko@arm.com", "time": "Tue Sep 27 15:23:43 2022 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Sep 30 14:24:33 2022 +0100" }, "message": "aarch64: enable access to HCRX_EL2\n\nAllow EL2 to access the HCRX_EL2 register which provides hypervisor\ncontrols similarly to HCR_EL2.\n\nSigned-off-by: Kristina Martsenko \u003ckristina.martsenko@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "6a0fc40035f9bb581054eb26fbac3c659cfa99b2", "tree": "ae1cb76369cbd111fa086565ee7c7980dbda7e52", "parents": [ "af0095532913adc06e9e0d1e842c2fbd8fda9167" ], "author": { "name": "Mark Brown", "email": "broonie@kernel.org", "time": "Tue Feb 01 17:21:32 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Feb 04 10:56:33 2022 +0000" }, "message": "aarch64: Enable use of SME by EL2 and below\n\nAllow lower ELs to use SME when booted on a system that support it. This\nrequires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set\nthe maximum vector length in a similar fashion to SVE and if the optional\nFA64 feature is present then set another feature bit in the new SMCR\nregister.\n\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n[Mark R: use BIT() for ID_AA64SMFR0_EL1_FA64, sort ID_AA64PFR1_EL1 fields]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20220201172132.2399026-2-broonie@kernel.org\n" }, { "commit": "af0095532913adc06e9e0d1e842c2fbd8fda9167", "tree": "c57bc44e0a861150caaa8904f6a582a4a8cc58a4", "parents": [ "6b8ae2f8b475c0ff242cedb7d459a604b5c1765c" ], "author": { "name": "Mark Brown", "email": "broonie@kernel.org", "time": "Tue Feb 01 17:21:31 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Feb 04 10:54:39 2022 +0000" }, "message": "aarch64: Document what we\u0027re doing when setting ZCR_EL3.LEN\n\nThe enumeration and configuration algorithm for SVE vector lengths is not\n100% obvious so add a comment explaining what\u0027s going on in case someone\nlooks at this code as a reference. If this is ever used on hardware with\nasymmetric vector lengths we will need to handle this differently to meet\nLinux\u0027s boot requirements but this is not a present issue and such hardware\nwould be fairly surprising.\n\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nLink: https://lore.kernel.org/r/20220201172132.2399026-1-broonie@kernel.org\n" }, { "commit": "6b8ae2f8b475c0ff242cedb7d459a604b5c1765c", "tree": "136fe0872125daa039d41fb2a4e8c78de09ff900", "parents": [ "ba0b47e844126992a7ced361301b74a995a5a5d6" ], "author": { "name": "Vladimir Murzin", "email": "vladimir.murzin@arm.com", "time": "Fri Jan 28 16:02:14 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Feb 01 12:18:05 2022 +0000" }, "message": "aarch64: Recognize PAuth QARMA3\n\nQARMA3 is relaxed version of the QARMA5 algorithm which expected to\nreduce the latency of calculation while still delivering a suitable\nlevel of security.\n\nSupport for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1]\n\nAPA3, bits [15:12] Indicates whether the QARMA3 algorithm is\n implemented in the PE for address authentication in\n\t\t AArch64 state.\n\nGPA3, bits [11:8] Indicates whether the QARMA3 algorithm is\n implemented in the PE for generic code\n authentication in AArch64 state.\n\n[1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang\u003den\n\nSigned-off-by: Vladimir Murzin \u003cvladimir.murzin@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "ba0b47e844126992a7ced361301b74a995a5a5d6", "tree": "907739db95e56e0f5f790578732af314487e7e5d", "parents": [ "3bce381552a8185dfd2fe9212fea7e2a9ee94d0e" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Jan 31 16:31:22 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Feb 01 12:03:30 2022 +0000" }, "message": "Makefile: avoid dtc warnings on re-compiling DTB\n\nWhen we add the PSCI nodes to the provided DTB, we use dtc to de-compile\nthe blob first, then re-compile it with our nodes and properties added.\n\nIn our input DTB the proper phandle references have already been lost,\nall we see in the DTB is phandle properties in the target node, and some\nnumbers in the clocks and gpios properties:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\tclk24mhz {\n\t\tcompatible \u003d \"fixed-clock\";\n\t\t#clock-cells \u003d \u003c0x00\u003e;\n\t\tclock-frequency \u003d \u003c0x16e3600\u003e;\n\t\tclock-output-names \u003d \"v2m:clk24mhz\";\n-\u003e\t\tphandle \u003d \u003c0x05\u003e;\n\t};\n\t...\n\tserial@90000 {\n\t\tcompatible \u003d \"arm,pl011\", \"arm,primecell\";\n\t\treg \u003d \u003c0x90000 0x1000\u003e;\n\t\tinterrupts \u003d \u003c0x05\u003e;\n-\u003e\t\tclocks \u003d \u003c0x05 0x05\u003e;\n\t\tclock-names \u003d \"uartclk\", \"apb_pclk\";\n\t};\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\ndtc warns that those numbers might be wrong:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003cstdin\u003e:177.6-27: Warning (clocks_property):\n /bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000:\n clocks: cell 0 is not a phandle reference\n....\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nThe proper solution would be to use references (\u0026v2m_clk24mhz) instead,\nas there are in the source .dts file, but we don\u0027t have that information\nanymore, and cannot easily recover it.\n\nTo avoid the lengthy list of warnings, just drop those checks from the\ndtc compilation run. This disables more checks than we want or need, but\nwe somewhat trust in the original DTB to be sane, so that should be\nfine.\nSince those warning options are not supported by older dtc versions,\nintroduce a compatiblity check before using them.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nTested-by: Vladimir Murzin \u003cvladimir.murzin@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "3bce381552a8185dfd2fe9212fea7e2a9ee94d0e", "tree": "0e60ba8a23ba09c563bbf0ff0070957513fd314e", "parents": [ "368a5c273e5cabaacf5d7319e0e52c43ced8a282" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Sep 29 15:26:48 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:14:49 2022 +0000" }, "message": "Unify start_el3 \u0026 start_no_el3\n\nNow that the start_el3 and start_no_el3 labels point at the same place,\nunify them into a start_bootmethod label and update callers.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "368a5c273e5cabaacf5d7319e0e52c43ced8a282", "tree": "991906677d9d0dda6586e6e4df0fa140ac9a31fc", "parents": [ "1c6ac5e25eda9c2743c042c8eb7a576b686f25b2" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 29 13:03:50 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:14:43 2022 +0000" }, "message": "Rework bootmethod initialization\n\nWe currently initialize the bootmethod late, in assembly code. This\nrequires us to maintain the el3/no_el3 distintion late into the boot\nprocess, and means we cannot produce any helpful diagnostic when booted\nat an unexpected exception level.\n\nRework things so that we initialize the bootmethod early, with a warning\nwhen things are wrong. The el3/no_el3 distinction is now irrelevant to\nthe bootmethod code, and can be removed in subsequent patches.\n\nWhen a boot-wrapper configured for PSCI is entered at EL2, a warning is\nlooged to the serial console as:\n\n| Boot-wrapper v0.2\n| Entered at EL2\n| Memory layout:\n| [0000000080000000..0000000080001f90] \u003d\u003e boot-wrapper\n| [000000008000fff8..0000000080010000] \u003d\u003e mbox\n| [0000000080200000..00000000822af200] \u003d\u003e kernel\n| [0000000088000000..0000000088002857] \u003d\u003e dtb\n|\n| WARNING: PSCI could not be initialized. Boot may fail\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "1c6ac5e25eda9c2743c042c8eb7a576b686f25b2", "tree": "1dfaffcfcbdd1de223719f1010c5d0e3125e28b2", "parents": [ "56b11458240b1ca9195d003ade17c725f7929050" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 23 16:19:20 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:14:23 2022 +0000" }, "message": "Announce locations of memory objects\n\nTo make it easier to debug boot failures, log the location of memory\nobjects at boot time.\n\nThis is logged to the serial console as:\n\n| Boot-wrapper v0.2\n| Entered at EL3\n| Memory layout:\n| [0000000080000000..0000000080001f90] \u003d\u003e boot-wrapper\n| [000000008000fff8..0000000080010000] \u003d\u003e mbox\n| [0000000080200000..00000000822af200] \u003d\u003e kernel\n| [0000000088000000..0000000088002857] \u003d\u003e dtb\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "56b11458240b1ca9195d003ade17c725f7929050", "tree": "3815c7e242dbe6236367f449563b39af548227bb", "parents": [ "352eeb8751ee3de8f76013f2e29a881917eec4cb" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 23 11:57:29 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:14:23 2022 +0000" }, "message": "aarch32: move the bulk of Secure PL1 initialization to C\n\nThe majority of state that we initialize at Secure PL1 is necessary for\ncode at lower PLs to function, but isnt\u0027 necessary for the boot-wrapper\nitself. Given that, it would be better to write this in C where it can\nbe written mode clearly, and where it will be possible to add\nlogging/debug logic.\n\nThis patch migrates the AArch32 Secure PL1 initialization to C.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "352eeb8751ee3de8f76013f2e29a881917eec4cb", "tree": "26c3c2671d70d03fb2c72289f3219975386b1bf9", "parents": [ "f11490d5d8d5a75d49d2b2f833bb6415f852bbfd" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 27 17:42:13 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:14:16 2022 +0000" }, "message": "aarch64: move the bulk of EL3 initialization to C\n\nThe majority of state that we initialize at EL3 is necessary for code at\nlower ELs to function, but isnt\u0027 necessary for the boot-wrapper itself.\nGiven that, it would be better to write this in C where it can be\nwritten mode clearly, and where it will be possible to add logging/debug\nlogic.\n\nThis patch migrates the AArch64 EL3 initialization to C.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "f11490d5d8d5a75d49d2b2f833bb6415f852bbfd", "tree": "281431a246b9e5b6b332b7682e9952980d55f009", "parents": [ "41498863d12f5eeff4b0ef16572fe7664ef8b713" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 28 17:18:49 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:13:59 2022 +0000" }, "message": "Announce boot-wrapper mode / exception level\n\nWhen something goes wrong within the boot-wrapper, it can be very\nhelpful to know where we started from. Add an arch_announce() function\nto log this early in the boot process. More information can be added\nhere in future.\n\nThis is logged ot the serial console as:\n\n| Boot-wrapper v0.2\n| Entered at EL3\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "41498863d12f5eeff4b0ef16572fe7664ef8b713", "tree": "21f72d552ab09c05d9d0c0626097fa6ae546b6e7", "parents": [ "10940859382ea345421d2d5c29a9475c8d7dc4b7" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 27 14:02:33 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:13:59 2022 +0000" }, "message": "Rework common init C code\n\nIn init_platform() we initialize a UART and announce the presence of the\nbootwrapper to the world. We do this relatively late in the boot-flow,\nand prior to this will silently ignore errors (e.g. in gic_secure_init).\n\nTo make it possible to provide improved diagnostics, and to allow us to\nmove more initialization into C, this patch reworks the init code to\ncall a C function earlier, where we can announce the presence of the\nboot-wrapper and perform other initialization.\n\nIn subsequent patches this will be expanded with more CPU\ninitialization.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "10940859382ea345421d2d5c29a9475c8d7dc4b7", "tree": "0a919aceaf2706c53ffad0c2c9245e7a10f4a02a", "parents": [ "df06a1f49df9f10542f308a2dba939ec16c0ec13" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 23 13:11:55 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:13:59 2022 +0000" }, "message": "aarch64: initialize SCTLR_ELx for the boot-wrapper\n\nThe SCTLR_ELx registers contain fields which are UNKNOWN or\nIMPLEMENTATION DEFINED out of reset. This includes SCTLR_ELx.EE, which\ndefines the endianness of memory accesses (e.g. reads from literal\npools). Due to this, portions of boot-wrapper code are not guaranteed\nto work correctly.\n\nRework the startup code to explicitly initialize SCTLR_ELx for the\nexception level the boot-wrapper was entered at. When entered at EL2\nit\u0027s necessary to first initialise HCR_EL2.E2H as this affects the RESx\nbehaviour of bits in SCTLR_EL2, and also aliases SCTLR_EL1 to SCTLR_EL2,\nwhich would break the initialization performed in jump_kernel.\n\nAs we plan to eventually support the highest implemented EL being any of\nEL3/EL2/EL1, code is added to handle all of these exception levels, even\nthough we do not currently support starting at EL1.\n\nWe\u0027ll initialize other registers in subsequent patches.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "df06a1f49df9f10542f308a2dba939ec16c0ec13", "tree": "af0aec69438c30f9fd6ce0d55befa9564fa9af98", "parents": [ "65113684081560a958726e392f400fdb23e2ccd6" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 23 10:44:36 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:13:59 2022 +0000" }, "message": "aarch64: add mov_64 macro\n\nIn subsequent patches we\u0027ll need to load 64-bit values into GPRs before\nthe CPU is in a known endianness, where we cannot use literal pools.\n\nIn preparation for that, this patch adds a new `mov_64` macro to load a\n64-bit value into a GPR using a sequence of MOV and MOVKs, which will\nfunction the same regardless of the CPU\u0027s endianness.\n\nAt the same time, move the `cpuid` macro to use `mov_64` internally.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "65113684081560a958726e392f400fdb23e2ccd6", "tree": "97084b729ca549a33c75581a533aefc0f0f0dd16", "parents": [ "9e2e06be7c8685171ee5ad285eda15d764e688e9" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 20 15:06:56 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:13:54 2022 +0000" }, "message": "aarch32: add coprocessor accessors\n\nWe open code the use of mrc/mcr for specific registers, which is\nsomewhat tedious. Add macros to do this generically, along with a helper\nto extract a specific register field. Existing C usage is converted to\nthe new helpers, and register definitions moved to a common location.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "9e2e06be7c8685171ee5ad285eda15d764e688e9", "tree": "fd55bcbe01da8b2efaf0531aeadcf4cb00a4c5e1", "parents": [ "d3b1a15d18542b2086e72bfdc3fc43f454772a3b" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 26 11:49:20 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:12:13 2022 +0000" }, "message": "aarch64: add system register accessors\n\nWe open code the use of mrs/msr for specific registers, which is\nsomewhat tedious. Add macros to do this generically, along with a helper\nto extract a specific register field. Existing C usage is converted to\nthe new helpers, and register definitions moved to a common location.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "d3b1a15d18542b2086e72bfdc3fc43f454772a3b", "tree": "d055aaeb19e6c44f462f9cd5ce7a0d9e8d5578c7", "parents": [ "286b8ecc86393c2619fc8e5792a4684c46fa461c" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 27 15:07:03 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:12:11 2022 +0000" }, "message": "Add bit-field macros\n\nArm architectural documentation typically defines bit-fields as\n`[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be\nhelpful if we could define fields in the same way.\n\nAdd helpers so that we can do so, along with helper to extract/insert\nbit-field values.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "286b8ecc86393c2619fc8e5792a4684c46fa461c", "tree": "35c6745c9f37844d838f650efc3d65e1b213ea9a", "parents": [ "2dc972a278766c44167f664eeca50e50dff8c511" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Aug 19 13:22:45 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 16:09:38 2022 +0000" }, "message": "Document entry requirements\n\nCurrently the boot-wrapper only supports some combinations of exception\nlevels, with other combinations not being supported.\n\nWhile we generally expect the boot-wrapper to be entered at the highest\nimplemented exception level, the AArch32 boot-wrapper has a comment\nimplying it supports being entered with something else owning EL3. As\nthis would require such EL3 firmware to always be in sync with the\nboot-wrapper\u0027s requirements, which change over time, we don\u0027t actually\nsupport such a configuration.\n\nSome CPU state (such as CNTFRQ/CNTFRQ_EL0) needs to be initialized at\nthe highest implemented exception level, but today the boot-wrapper only\ndoes so when entered at EL3 / Secure-PL1. Thus, today the only\ncompletely supported configurations are EL3 / Secure-PL1, and entering\nin other configurations is not entirely supported.\n\nThe aarch64 `jump_kernel` function always writes to SCTLR_EL2, which is\nUNDEFINED at EL1. Hence, the aarch64 boot-wrapper does not support being\nentered at EL1.\n\nThe aarch32 code assumes that any non-hyp mode is Secure PL1, and\nattempt to switch to monitor mode. If entered on a system without the\nsecurity extensions, where the highest privileged mode is Non-secure\nPL1, this will not work. Hence the aarch32 boot-wrapper does not support\nbeing entered at Non-secure PL1.\n\nActually supporting all of these configurations requires restructuring\nmuch of the boot-wrapper. For now, document the supported configurations\nin each architecture\u0027s boot.S, and remove the misleading comment from\narch/aarch32/boot.S. Subsequent patches will improve the support and add\nsupport for additional configurations.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "2dc972a278766c44167f664eeca50e50dff8c511", "tree": "b6a126634597e29bca7cfe76e6a706ea20537124", "parents": [ "2dd9f3117d00b4d78e7a2e5309140b11f5f5ac07" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jan 25 14:16:41 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 15:51:45 2022 +0000" }, "message": "aarch64: correct SCTLR_EL1_KERNEL for AA32 kernels\n\nBits [31:0] of the AArch64 SCTLR_EL1 register are architecturally mapped\nto bits [31:0] of the AArch32 SCTLR register. This means that any\nindividual bit always has the same value across the two registers.\n\nAcross the two registers, the same bit may have distinct meanings,\ndistinct RESx behaviour, and distinct reset behaviour. For example,\nSCTLR_EL1[28] is nTLSMD, which we wich to initialize to 0b1, whereas\nSCTLR[28] is TRE, which we wish to initialize to 0b0.\n\nTo avoid setting bits which we did not intend to, and in preparation for\nconfiguring more AArch64 RES1 bits, this patch decouples the\nSCTLR_EL1_KERNEL value used for AArch32 kernels from the SCTLR_EL1_RES1\ndefinitions such that is does not inherit AArch64 SCTLR_EL1 bits which\nwould be problematic in the AArch32 SCTLR. For now we open-code a copy\nof the bits defined in arch/aarch64/include/asm/cpu.h.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "2dd9f3117d00b4d78e7a2e5309140b11f5f5ac07", "tree": "d1f42b5c9ae4371249661534b448fa4e8488d522", "parents": [ "0607f1669cd66442cc956ff174db679971e14613" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jan 19 15:05:15 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 27 15:49:20 2022 +0000" }, "message": "aarch64: correct ZCR_EL3.LEN initialization\n\nThe ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are\nRAZ/WI, likely so that in future these can be used to extend LEN without\ncomplicating the probing of the maximum available vector length.\n\nCurrently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN\nfield and the RAZ/WI bits.\n\nTo match the architecture as documented, reduce this down to 0xf, only\ncovering the bits currently allocated to the LEN field. We can extend\nthis in future if the LEN field is widened.\n\nAs the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is\nused as a value rather than as a bit mask.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\n" }, { "commit": "0607f1669cd66442cc956ff174db679971e14613", "tree": "6d0cbba0f8ebf05e8fac1c29bef3072754e477a4", "parents": [ "9aa732349371056da2ca90b03468bc1c8e0016e2" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jan 19 11:52:33 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jan 19 11:52:49 2022 +0000" }, "message": "Revert \"avoid dtc warnings on re-compiling DTB\"\n\nAs Vladimir Murzin reports in:\n\n https://lore.kernel.org/linux-arm-kernel/706471d8-a0fd-35fb-4fa0-380bfb1b78e7@arm.com/\n\nOlder version of dtc don\u0027t support the options to suprress the warnings,\nand so where people are stuck with said versions of dtc, using those\noptions results in a build failure rather than an ignoreable build\nwarning.\n\nFor now, let\u0027s revert the warning suppression. In future we can try to\ndo something smarter.\n\nThis reverts commit 1044c77062573985f7c994c3b6cef5695f57e955.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "9aa732349371056da2ca90b03468bc1c8e0016e2", "tree": "b58a88c8293ce638d499ad761a84327c30dcaaba", "parents": [ "16bca1c4147f6906f76d8961a09bf1682399d70f" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Thu Jan 13 15:11:08 2022 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jan 18 10:31:06 2022 +0000" }, "message": "aarch64: Enable BRBE for the non-secure world\n\nMDCR_EL3.SBRBE resets to an UNKNOWN value. Configure it to allow the BRBE\nbuffer usage and direct register access in the non-secure world. But just\nbefore that, check AA64DFR0_EL1.BRBE and make sure BRBE is implemented. We\nstill continue to reset MDCR_EL3 register to zero with the exception of\nMDCR_EL3.NSPB, MDCR_EL3.NSTB and MDCR_EL3.SBRBE.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "16bca1c4147f6906f76d8961a09bf1682399d70f", "tree": "ca8886e1d7391816c308353108b921ccbf02df86", "parents": [ "1044c77062573985f7c994c3b6cef5695f57e955" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Jan 17 15:33:48 2022 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jan 17 17:11:53 2022 +0000" }, "message": "Makefile: Tell compiler to generate bare-metal code\n\nOur GCC invocation does not provide many parameters, which lets the\ntoolchain fill in its own default setup.\nIn case of a native build or when using a full-featured cross-compiler,\nthis probably means Linux userland, which is not what we want for a\nbare-metal application like boot-wrapper.\n\nTell the compiler to forget about those standard settings, and only use\nwhat we explicitly ask for. In particular that means to not use toolchain\nprovided libraries, since they might pull in more code than we want, and\nmight not run well in the boot-wrapper environment.\n\nDisable the stack protector, as this relies on support code, e.g.\na __stack_chk_guard variable and __stack_chk_fail function, which the\nboot-wrapper does not implement.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "1044c77062573985f7c994c3b6cef5695f57e955", "tree": "8e679506df1af63922dc4bdce695ac8d39b192a9", "parents": [ "fa754a55b3363266a999ef41dddc7a74a37a34cd" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:16:07 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:15:56 2022 +0000" }, "message": "avoid dtc warnings on re-compiling DTB\n\nWhen we add the PSCI nodes to the provided DTB, we use dtc to de-compile\nthe blob first, then re-compile it with our nodes and properties added.\n\nIn our input DTB the proper phandle references have already been lost,\nall we see in the DTB is phandle properties in the target node, and some\nnumbers in the clocks and gpios properties:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\tclk24mhz {\n\t\tcompatible \u003d \"fixed-clock\";\n\t\t#clock-cells \u003d \u003c0x00\u003e;\n\t\tclock-frequency \u003d \u003c0x16e3600\u003e;\n\t\tclock-output-names \u003d \"v2m:clk24mhz\";\n-\u003e\t\tphandle \u003d \u003c0x05\u003e;\n\t};\n\t...\n\tserial@90000 {\n\t\tcompatible \u003d \"arm,pl011\", \"arm,primecell\";\n\t\treg \u003d \u003c0x90000 0x1000\u003e;\n\t\tinterrupts \u003d \u003c0x05\u003e;\n-\u003e\t\tclocks \u003d \u003c0x05 0x05\u003e;\n\t\tclock-names \u003d \"uartclk\", \"apb_pclk\";\n\t};\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\ndtc warns that those numbers might be wrong:\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003cstdin\u003e:177.6-27: Warning (clocks_property):\n /bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000:\n clocks: cell 0 is not a phandle reference\n....\n\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\nThe proper solution would be to use references (\u0026v2m_clk24mhz) instead,\nas there are in the source .dts file, but we don\u0027t have that information\nanymore, and cannot easily recover it.\n\nTo avoid the lengthy list of warnings, just drop those checks from the\ndtc compilation run. This disables more checks than we want or need, but\nwe somewhat trust in the original DTB to be sane, so that should be\nfine.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "fa754a55b3363266a999ef41dddc7a74a37a34cd", "tree": "925b945bd61d0facdd477aa66cafd62ad969794e", "parents": [ "1d2f934679b60b2f4095c3f132d3b0e7ef9d9717" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:16:05 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:10:13 2022 +0000" }, "message": "pointer auth: Document CPU feature bit mask\n\nWhen checking for the pointer authentication feature, we actually look\nfor *four* different CPUID feature sets.\nAdd a comment to make it more obvious that the 0xff is not a typo.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "1d2f934679b60b2f4095c3f132d3b0e7ef9d9717", "tree": "ae8b1e7b89acf1a8f86c1b468811ac1dd821c3ce", "parents": [ "4c2d1420230ad0e41b79b6b225450645732f885a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:16:04 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:10:13 2022 +0000" }, "message": "configure: Use earlycon instead of earlyprintk\n\nThe arm64 Linux kernel dropped support for the \"earlyprintk\" command line\nparameter a long time ago[1], instead it uses the earlycon parameter\nnow.\n\nReplace earlyprintk with earlycon on the default command line, to see\nearly kernel output.\n\nIdeally we would just say \"earlycon\" (without specifying an MMIO\naddress), but this relies on the stdout-path property in the /chosen\nnode, which the model DTs do not carry.\n\n[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id\u003d8ef0ed95ee04\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "4c2d1420230ad0e41b79b6b225450645732f885a", "tree": "75f3fbee366d1ab7e3146330e27f0b8f23158ce7", "parents": [ "0212217866e20e6fc9d59dad843b0bca47ff0212" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:16:03 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:10:13 2022 +0000" }, "message": "configure: Fix default DTB\n\nThe DTS files for Arm Ltd. boards and the fastmodel have long been moved\ninto the arm/ subdirectory of the arm64 kernel tree\u0027s DT folder.\n\nAdjust the default path to make this build out of the box.\n\nAlso change the default DTB to the more modern FVP RevC model on the\nway.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "0212217866e20e6fc9d59dad843b0bca47ff0212", "tree": "13908dc00cae8ec39af7517807e95628a11e9e47", "parents": [ "66cc36c96e9a91e613734cf595e8c3212128e233" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:16:02 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:10:13 2022 +0000" }, "message": "configure: Make PSCI the default boot method\n\nWhen the boot-wrapper was originally conceived, PSCI was a rather new\nfeature, so support in contemporary kernels wasn\u0027t guaranteed. The\nboot-wrapper consequently defaulted to not using PSCI.\n\nFortunately the times have changed, and most people expect PSCI these\ndays, so let\u0027s enable PSCI by default.\n\nWe keep the --enable-psci/--disable-psci configure switch, so it can be\nstill turned off if needed.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "66cc36c96e9a91e613734cf595e8c3212128e233", "tree": "5cdbadd78133ed69df7dc9e577c064e2ea991f2c", "parents": [ "28932c41e14d730b8b9a7310071384178611fb32" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Dec 22 18:15:59 2021 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jan 07 14:07:30 2022 +0000" }, "message": "Makefile: Avoid .got section creation\n\nAt the moment we build the boot-wrapper with the default toolchain\nsettings, which has issues if that is a toolchain targeted to Linux\nuserland, for instance. Since boot-wrapper is rather simple, we get away\nwith this, *mostly*, but there is at least one case where this breaks:\nMany distributions enable PIE builds by default when building GCC, so by\njust calling \"gcc\" we build the .o files for PIE (although we don\u0027t link\nthem accordingly, since we use \"ld\" directly).\nWhen we moved the PSCI code from assembly to C, we also introduced\nglobal variables, which a PIE enabled GCC will put into a .got section\n(global offset table), to be able to easily relocate them at runtime\n(if needed). This section happens to be outside of the memory region\nwe reserve, so can (and will be) overwritten by Linux at some point.\nDoing PSCI calls afterwards does not end well then. \"memtest\u003d1\" is one\nway to trigger this.\n\nTo avoid the (in our case pointless) creation of the GOT, we specify\n-fno-pic and -fno-pie, to override any potential toolchain default.\n\nThis fixes boot-wrapper builds on many distro compilers, for instance\nas provided by Ubuntu and Arch Linux.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "28932c41e14d730b8b9a7310071384178611fb32", "tree": "85dc54fc22af1de849cd193025ab0f58d0e13f60", "parents": [ "c96e46f4d24370202f4e1088f046537baacea0e8" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 23 11:42:47 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 25 10:48:39 2021 +0100" }, "message": "Rename `CNTFRQ` -\u003e `COUNTER_FREQ`\n\nTo avoid any confusuion between the CNTFRQ/CNTFRQ_EL0 register and the\nvallue it will be progrmamed with, rename the `CNTFRQ` constant to\n`COUNTER_FREQ.\n\nIn future patches this will allow us to use `CNTFRQ` as a macro for the\nAArch32 CP15 register encoding.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\n" }, { "commit": "c96e46f4d24370202f4e1088f046537baacea0e8", "tree": "0ccf6780b23b34ce82b179559ea28c96a6231e89", "parents": [ "301abde2d4736f647df6cbf4cc60619b09cd0b7b" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 23 11:01:11 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 25 10:48:32 2021 +0100" }, "message": "Rename kernel *_RESET values to *_KERNEL\n\nOur *_RESET constants are used to initalize state for the kernel rather\nthan the bootwrapper itself, so for clarity we should use a *_KERNEL\nsuffix rather than a _RESET suffix.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\n" }, { "commit": "301abde2d4736f647df6cbf4cc60619b09cd0b7b", "tree": "c7961e234520a22bebfdb4bea988a761d951fb4f", "parents": [ "776291ee8ee4f62215867f663fb34e1fef13289e" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jul 30 10:17:11 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 25 10:48:21 2021 +0100" }, "message": "GICv3: initialize without RMW\n\nThere\u0027s no need to perform an RMW sequence to initialize ICC_SRE_EL3, as\nthere are no bits that we need to preserve, and generally we should\nreset registers to specific values such that RESx bits aren\u0027t configured\nto UNKNOWN values that could be problematic in future architecture\nversions.\n\nInstead, let\u0027s initialize ICC_SRE_EL3 with a constant value. Since the\n`DIB` and `DFB` fields are RAO/WI in some configurations and we have no\nreason to initialize these to 0, we always initialize these to 1, in\naddition to `SRE` and `SRE_Enable`.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nCc: Alexandru Elisei \u003calexandru.elisei@arm.com\u003e\n" }, { "commit": "776291ee8ee4f62215867f663fb34e1fef13289e", "tree": "0f96f9eff02cddd4173180c636f9e64b3996a94e", "parents": [ "325f6ccc9be91137630cbcad988be82473ab0eeb" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Aug 19 18:37:28 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 25 10:48:16 2021 +0100" }, "message": "aarch32: simplify _switch_monitor\n\nIf we\u0027re lucky enough to have been booted into secure PL1, we can switch\nto monitor mode with an exception return rather than an SMC call, which\navoids the need for boot-time vectors.\n\nNote that while all Secure PL1 register state is accessible in Secure\nSVC mode, we must switch to Monitor mode before we set SCR.NS\u003d1.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\n" }, { "commit": "325f6ccc9be91137630cbcad988be82473ab0eeb", "tree": "c3a419a0a397c61b63b2244550c5025f8d05d22e", "parents": [ "5cd6238ec4ef97687eeea9e011db0d6305216543" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Aug 20 14:51:33 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 25 10:47:53 2021 +0100" }, "message": "Remove unused Set/Way cache helpers\n\nWe removed the Set/Way cache maintenance in commit:\n\n 864182b26c20a39d (\"Remove cache maintenance\")\n\n... but forgot to remove the arch helpers which are now unused.\n\nRemove the unused helpers.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\n" }, { "commit": "5cd6238ec4ef97687eeea9e011db0d6305216543", "tree": "679570ba3f7417d328ae0f452837f6d1e952220d", "parents": [ "ada217d48ba82906028042a53f12905c1107addf" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Aug 19 17:01:26 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Aug 19 17:09:01 2021 +0100" }, "message": "aarch32: fix .globl replacement\n\nIn commit:\n\n fcb8a82b91a39ce2 (\"Cleanup `.globl` usage\")\n\n... we forgot to include \u003clinkage.h\u003e in asm/stack.S, and consequently\nbroke the build as the assembler has no idea what ASM_FUNC() and\nASM_DATA() mean.\n\nAdd the missing include.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "ada217d48ba82906028042a53f12905c1107addf", "tree": "81121fd5e5abeb31df7d08ef3d5e5b53202ca35a", "parents": [ "bc6a9380eb3c5afc96735a54d455f2487df48700" ], "author": { "name": "Alexandru Elisei", "email": "alexandru.elisei@arm.com", "time": "Tue Aug 17 17:34:20 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 18 15:12:30 2021 +0100" }, "message": "aarch64: Do not trap PMSNEVFR_EL1\n\nFEAT_PMUv1p2 adds a new register, PMSNEVFR_EL1, and a new MDCR_EL3 trap bit\nfor it, EnPMSN. Set the bit to 1 to allow lower exception levels direct\naccess to the register.\n\nSigned-off-by: Alexandru Elisei \u003calexandru.elisei@arm.com\u003e\n[Mark: use ORR (Imm) to enable SPE, use 1f label, re-order comment]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "bc6a9380eb3c5afc96735a54d455f2487df48700", "tree": "c07dffe1ef7cfbe9793fbf1cf040829ee098ec90", "parents": [ "f8fc0c92e5bc22d2acc8ea82453cbddbb5e822e3" ], "author": { "name": "Marc Zyngier", "email": "maz@kernel.org", "time": "Wed Aug 11 10:22:26 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 11 14:53:24 2021 +0100" }, "message": "aarch64: Enable ECV to allow access to CNTPOFF_EL2\n\nIf the implemnentation supports ID_AA64MMFR0_EL1.ECV\u003d\u003d2,\nset SCR_EL3.ECVEn to allow EL2 access to CNTPOFF_EL2.\n\nSigned-off-by: Marc Zyngier \u003cmaz@kernel.org\u003e\n[Mark: read id_aa64mmfr0_el1 separately, s/bne/b.lt/]\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "f8fc0c92e5bc22d2acc8ea82453cbddbb5e822e3", "tree": "3fd2a0fd492c0564140dbb97ad98fd01501e022f", "parents": [ "378bbbec05c5c1d8b136ecd3a487e6f60d119c83" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 26 14:46:01 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Move common source files to `common` directory\n\nThe top-level directory is getting increasingly cluttered. For clarity\nlet\u0027s move the common source files into their own directory. At the same\ntime let\u0027s clean up the way we generate object lists so that it\u0027s\nconsistent for arch/common objects, and doesn\u0027t require special casing\neach optional object.\n\nNote that we also need to create a common/ directory for out-of-tree\nbuilds.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "378bbbec05c5c1d8b136ecd3a487e6f60d119c83", "tree": "46f4f8fb57fe546f34ab5ca206e3f208de652e5e", "parents": [ "a003b043db9bc9d09b8273817b7b1ece1efd7d87" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 29 10:25:10 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Rename `spin.h` -\u003e `boot.h`\n\nIn `spin.h` we have function prototypes provided by `boot.c`. For\nclarity, let\u0027s align the naming.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a003b043db9bc9d09b8273817b7b1ece1efd7d87", "tree": "3924aed4a4e22a49692136ccf6916bb1dec530bc", "parents": [ "fcb8a82b91a39ce2f21fdd712f81f09f66ad48cb" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 28 13:30:39 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "aarch32: rename `_spin_dead` -\u003e `err_invalid_id`\n\nFor clarity, align aarch32 with aarch64, sending unexpected CPUs to an\n`err_invalid_id` loop rather than `_spin_dead`.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "fcb8a82b91a39ce2f21fdd712f81f09f66ad48cb", "tree": "dc6b2eced36059049640f21538b660bbad7b2509", "parents": [ "587b1c6e4c7104630d8353520bbc66bb0e235bbc" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 29 10:55:00 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Cleanup `.globl` usage\n\nIn some places we use `ENTRY()` to mark an assembly function, whereas in\nothers we just use `.globl`. Where we use `.globl` for functions or\ndata, we don\u0027t keep this close to the actual definition.\n\nFurther, `ENTRY()` is a keyword in linker script with a different\nmeaning, and so it would be nicer if we didn\u0027t use the same term in the\nassembly files.\n\nThis patch adds `ASM_FUNC()` and `ASM_DATA()` markers, and uses them\nconsistently throughout the codebase.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "587b1c6e4c7104630d8353520bbc66bb0e235bbc", "tree": "6d2219ce98eea55a373a730b05addeb1c551bac3", "parents": [ "4a50f69c550473b989f0d38f096d4d9a3a6804c7" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 27 14:14:14 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Consistently use logical CPU IDs\n\nIn some places we assume that the cpu with MPIDR_EL1.Aff* \u003d\u003d 0 is the\nsame as logical CPU 0. While this is almost certainly true, it would be\nbest to consistently use the logical ID.\n\nAdd a new `this_cpu_logical_id()` helper, and use this in preference to\nchecking the MPIDR_EL1.Aff* bits directly.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "4a50f69c550473b989f0d38f096d4d9a3a6804c7", "tree": "331525a04ae36409fb33474e38dd247658ea5c72", "parents": [ "9a730aac690fe329dddbb401d66e7c41d57889c2" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 26 14:10:38 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "aarch64: respect text offset\n\nThe boot-wrapper assumes that an AArch64 kernel\u0027s text offset is 0x80000\nrather than reading the `text_offset` field from the Image header as the\ndocumentation says it should.\n\nAdd a script to figure this out during the build process. As with FDT.pm\nthe parsing of the Image (and common logic associated with this) is\nfactored into a module that we may use in more scripts in future.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "9a730aac690fe329dddbb401d66e7c41d57889c2", "tree": "1a851f66fd493b65cba5232de2b6c1905655b236", "parents": [ "a68fa4856fb0fb9e1c8cabbb0937fca20cc47cd4" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jul 26 12:31:08 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Move scripts to a `scripts` directory\n\nThe top-level directory is getting increasingly cluttered. For clarity\nlet\u0027s move the scripts into their own directory.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a68fa4856fb0fb9e1c8cabbb0937fca20cc47cd4", "tree": "3badcff0254e230e1c4847fec2b8966a9e631d4b", "parents": [ "864182b26c20a39d334729dac1cc489737ff7014" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 28 15:53:05 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:36:52 2021 +0100" }, "message": "Move PSCI triage to C\n\nThere\u0027s no reason we need to test the PSCI function IDs in assembly;\nmove this to C so that it can be shared across AArch64 and AArch32. At\nthe same time, limit the PSCI_CPU_ON FIDs to match the register width of\nthe kernel.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "864182b26c20a39d334729dac1cc489737ff7014", "tree": "6d695e739ee3db14f3730d279205e7f3b9966ef4", "parents": [ "0d024605dd2e831c9adb76799c44700e37c37cca" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Jul 28 10:49:40 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:27:57 2021 +0100" }, "message": "Remove cache maintenance\n\nFor models, we assume that out-of-reset caches are invalid and no cache\nmaintenance is required.\n\nWe added cache maintenance to the boot-wrapper in commit:\n\n 28ec269a22c8dc14 (\"Add code to clean and invalidate caches\")\n\n... because the boot-wrapper would transiently use cacheable mappings,\nand could allocate into caches. As we were using Set/Way operations, we\nwere on somewhat shaky ground (e.g. due to system-level caches, or\ndirty line migration). Further, we never took FEAT_CCIDX into account,\nand so would not necessarily invalidate all potential levels of cache\n\nHowever, since commit:\n\n 0bb7b2545582accf (\"Remove MMU identity map setup\")\n\n... we no longer enable the MMU within the boot-wrapper, and so no\nlonger have any reason to perform cache maintenance.\n\nThis patch removes the redundant and incomplete cache maintenance.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "0d024605dd2e831c9adb76799c44700e37c37cca", "tree": "b17746e442d4b1e7f37bbdf4dbcc45900658f8f8", "parents": [ "c1a09cc66c1efe18f06f924609f8798d328af2bc" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 29 12:42:01 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:27:57 2021 +0100" }, "message": "Output text separately from data\n\nAssembly files generally assume that .text is word-aligned, and don\u0027t\nexplciitly align the .text section. However, if we mix .text with data\nsections at link time, we can output .text sections at less than word\nalignment, resulting in boot-time hangs that are painful to debug.\n\nOutput all .text sections before .data sections to minimize this risk.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "c1a09cc66c1efe18f06f924609f8798d328af2bc", "tree": "f897c8bbab445935af5a72e150dcda2bd8f8d3f0", "parents": [ "cf13c653db78c849ac404a89e54f25d47154bd83" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 29 14:42:19 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:27:57 2021 +0100" }, "message": "Ensure `kernel_address` is aligned\n\nWe accidentally placed the `.align` directive after the `kernel_address`\nlabel, meaning that the label itself isn\u0027t necessarily aligned. Place\nthe `.align` directive first to ensure this.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "cf13c653db78c849ac404a89e54f25d47154bd83", "tree": "426d83a6f9927f70618eb20a6b63ff8cb5ccd322", "parents": [ "3728ea63cd051991be019ae07601b4b9a4f21a0b" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon May 10 13:07:24 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 02 15:27:40 2021 +0100" }, "message": "Fix arch counter frequency\n\nAs the comment states, the frequency of the Generic Timer in the model\nis 24 MHz, and not the currently used 0x1800000, which is actually\n25,165,824 (~5% higher).\n\nUse the proper number, and not something power-of-2 based.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "3728ea63cd051991be019ae07601b4b9a4f21a0b", "tree": "ea05c7f52904b1350ce0c85aed0fb039dfeabe49", "parents": [ "114a9fa2e031f94821d96b1b8b2fc6d5e7b60a51" ], "author": { "name": "Jaxson Han", "email": "jaxson.han@arm.com", "time": "Tue May 25 14:25:02 2021 +0800" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 22 11:30:09 2021 +0100" }, "message": "Decouple V2M_SYS config by auto-detect dtb node\n\nAn auto-detect switch is added to make it an option to enable/disable\n\u0027arm,vexpress-sysreg\u0027, because not all platforms support this feature.\n\nBut the auto-detection generates the side-effect of printing a warning\nmessage about the missing node:\nNo matching devices found at ./findbase.pl line 37.\n\nIn this case, to drop the warning message, add \"2\u003e /dev/null\" at the\nend of the findbase.pl call.\n\nSigned-off-by: Jaxson Han \u003cjaxson.han@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "114a9fa2e031f94821d96b1b8b2fc6d5e7b60a51", "tree": "7b63a1ef0ee96d1bb53f1bfe5bb5a196b166389a", "parents": [ "05347efa932c34b8ab332f5b829f57a2a9ace91b" ], "author": { "name": "Jaxson Han", "email": "jaxson.han@arm.com", "time": "Tue May 25 14:25:04 2021 +0800" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jul 22 11:30:07 2021 +0100" }, "message": "aarch64: Remove the redundant setup_stack\n\nSince we already have set up a stack above, there is no need to do it\nagain.\nAlso, in fact it\u0027s a bug: setup_stack expects the logical CPU ID in\nw0, and here we always call it with w0 being 1.\n\nSigned-off-by: Jaxson Han \u003cjaxson.han@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "05347efa932c34b8ab332f5b829f57a2a9ace91b", "tree": "76fa36493dfd5337c13f65b69b979cb93f14e17a", "parents": [ "9a9f85ce6f128125d2b5ee3700e36fb89d31cdc0" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed May 05 10:38:55 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu May 06 09:22:03 2021 +0100" }, "message": "aarch64: Enable access to allocation tags if MTE is present\n\nSCR_EL3.ATA must be set so that software can access the allocation\n(in-memory) MTE tags.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "9a9f85ce6f128125d2b5ee3700e36fb89d31cdc0", "tree": "1456075e952ff4433498a392be690d1f646ba979", "parents": [ "22fc09cddd96dda9118faaa5c734e59949d9ae41" ], "author": { "name": "Marc Zyngier", "email": "maz@kernel.org", "time": "Mon May 03 13:09:20 2021 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue May 04 16:23:47 2021 +0100" }, "message": "aarch64: Enable FGT for EL2\n\nWe have no intention of handling FGT traps to EL3, so let EL2\nplay with the feature directly.\n\nSigned-off-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "22fc09cddd96dda9118faaa5c734e59949d9ae41", "tree": "dcd378768d302c93666f4b587cd3e6a18da18aaf", "parents": [ "8d5a765251d9113c3c0f9fa14de42a9e7486fe8a" ], "author": { "name": "Anshuman Khandual", "email": "anshuman.khandual@arm.com", "time": "Thu Feb 11 16:56:37 2021 +0530" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Feb 25 18:28:24 2021 +0000" }, "message": "aarch64: Enable TRBE for the non-secure world\n\nMDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace\nbuffer to use non-secure memory and to permit direct register accesses from\nthe non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and\nmake sure TRBE is implemented. We still continue to reset MDCR_EL3 register\nto zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.\n\nSigned-off-by: Anshuman Khandual \u003canshuman.khandual@arm.com\u003e\nReviewed-by: Alexandru Elisei \u003calexandru.elisei@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "8d5a765251d9113c3c0f9fa14de42a9e7486fe8a", "tree": "3fe2034644bacedf756e6c82da62344a980ff6ee", "parents": [ "fd74c8cbd0e17483d2299208cad9742bee605ca7" ], "author": { "name": "Alexandru Elisei", "email": "alexandru.elisei@arm.com", "time": "Fri Jul 31 10:44:43 2020 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Aug 12 13:06:04 2020 +0100" }, "message": "aarch64: Enable SPE for the non-secure world\n\nMDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the\nprofiling buffer to use non-secure memory and to permit direct register\naccesses from the non-secure world.\n\nSo far, we haven\u0027t programmed MDCR_EL3 explicitly even though there are\nother fields which reset to an UNKNOWN value. The majority of those, when\ncleared, allow lower exception levels to use the features they control; for\nthe other fields we don\u0027t have support yet. Reset the register to zero\nwith the exception of MDCR_EL3.NSPB.\n\nSigned-off-by: Alexandru Elisei \u003calexandru.elisei@arm.com\u003e\nReviewed-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "fd74c8cbd0e17483d2299208cad9742bee605ca7", "tree": "77ced595c5298d3ed5d097c9386c22b4553bba91", "parents": [ "c11fd1e6e65399244b14d3f3d9052e2e5b7b943d" ], "author": { "name": "Will Deacon", "email": "will@kernel.org", "time": "Fri Aug 23 15:50:15 2019 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 27 12:04:01 2019 +0100" }, "message": "Enable TME for lower exception levels\n\nBy default, TME is not available to exception levels below EL3, so\nenable it in SCR_EL3 if we detect that it is implemented.\n\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "c11fd1e6e65399244b14d3f3d9052e2e5b7b943d", "tree": "c7056f30547ace7517033362e943986da7d7e1b5", "parents": [ "ed60963595855e66ffc06a8a543cbb429c7ede03" ], "author": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Tue Jul 23 16:00:04 2019 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 23 16:47:59 2019 +0100" }, "message": "Make GICv3.1 extended ranges available to non-secure\n\nIf we have a GICv3.1-capable system, configure the EPPI/ESPI ranges\nto be accessible from the non-secure world.\n\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "ed60963595855e66ffc06a8a543cbb429c7ede03", "tree": "1d3d4aec58f52ff6643f254a8b955dbafad62a3c", "parents": [ "c7904c2dee7af838ec08131ecdfe74d4e43a49f9" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 05 10:59:33 2017 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 26 14:18:58 2018 +0100" }, "message": "Enable pointer auth for EL2 and below\n\nBy default, use of pointer authentication functionality (either\ninstructions or access to keys) will trap to EL3.\n\nThis patch programs SCR_EL3 to enable pointer authentication for lower\nexception levels.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "c7904c2dee7af838ec08131ecdfe74d4e43a49f9", "tree": "b44816279bd98a1ef45dc13aa9de6c2343b158c2", "parents": [ "7c2bc5495e556c9039f0d3e79d8d5af4ad35baf4" ], "author": { "name": "Jean-Philippe Brucker", "email": "jean-philippe.brucker@arm.com", "time": "Mon Apr 23 17:32:06 2018 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 26 13:54:29 2018 +0100" }, "message": "Fix out-of-tree build\n\nAdding AArch32 support to the boot-wrapper changed the source layout and\nbroke out-of-tree build. This patch allows to put all generated files\ninto a separate directory again, and build multiple images in parallel:\n\n mkdir build/ \u0026\u0026 cd build/\n ~/src/boot-wrapper-aarch64/configure ...\n make\n\nMake attempts to output object files into build/arch/aarchXX/, but fails\nbecause that folder doesn\u0027t exist in the build directory. Add mkdir as\nprerequisite for any *.o target in the arch folder.\n\nSo that Make doesn\u0027t confuse the destination folder with the source,\noverride VPATH to only affect .S and .c sources.\n\nAnd set $(ARCH_SRC) as order-only-prerequisite (after a \u0027|\u0027). Otherwise\nMake would rebuild all objects whenever the timestamp of $(ARCH_SRC)\nchanges, which is every time an object is rebuilt...\n\nSigned-off-by: Jean-Philippe Brucker \u003cjean-philippe.brucker@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "7c2bc5495e556c9039f0d3e79d8d5af4ad35baf4", "tree": "b3efb21916ff7ced1a7e1ed823c8f5a315177354", "parents": [ "5e1261e08abfb8add6491b90a42076e864589ced" ], "author": { "name": "Suzuki K Poulose", "email": "suzuki.poulose@arm.com", "time": "Wed Apr 25 14:06:04 2018 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 26 13:52:58 2018 +0100" }, "message": "boot-wrapper-aarch64: Do not hardcode TEXT_LIMIT\n\nWe hard code TEXT_LIMIT to check for image overflow, assuming the memory\nis always at 0x80000000, which may not always be true. Instead use the\noffset from the PHYS_OFFSET, which is actually dependent on the DT.\n\nSigned-off-by: Suzuki K Poulose \u003csuzuki.poulose@arm.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "5e1261e08abfb8add6491b90a42076e864589ced", "tree": "8ddb163e6674dcd8ed9139e605d6ef8fdcb700b0", "parents": [ "ccdc936924b3682db547eb90519cfe7cebd785ed" ], "author": { "name": "Dave Martin", "email": "Dave.Martin@arm.com", "time": "Wed Sep 20 13:09:48 2017 +0100" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Sep 20 13:41:29 2017 +0100" }, "message": "bootwrapper: SVE: Enable SVE for EL2 and below\n\nBy default, SVE will trap to EL3. We also want to make sure that\nlower ELs have access to the full SVE vector length before dropping\ndown.\n\nThis patch programs CPTR_EL3 and ZCR_EL3 appropriately to enable\nSVE for lower exception levels and make sure that they can use the\nfull vector length provided by the hardware.\n\nSigned-off-by: Dave Martin \u003cDave.Martin@arm.com\u003e\nCc: Alex Bennée \u003calex.bennee@linaro.org\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "ccdc936924b3682db547eb90519cfe7cebd785ed", "tree": "c2cc22c340219c7d342d50f01efafc397d3717f1", "parents": [ "6e7aa16562f8ac0a98087d48985b2f4a909e414f" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 19 15:09:32 2017 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Feb 17 12:11:55 2017 +0000" }, "message": "Dynamically determine the set of CPUs\n\nCurrently we hard-code the set of CPUs we expect, and we have some\nstrong expectations on the formatting of nodes.\n\nAs we can configure models with differing sets of CPUs, we added the\nwith-cpu-ids configure option to override this assumption, though in\npractice it turns out this is very fragile.\n\nInstead, we can parse the DTB to discover the set of CPU nodes (and\nhence the set of CPU IDs, and the number of CPUs). This is far more\nrobust.\n\nThis patch changes the bootwrapper to do this, removing the newly\nredundant --with-cpu-ids configure option.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" }, { "commit": "6e7aa16562f8ac0a98087d48985b2f4a909e414f", "tree": "4f98bc30666896cf26b6f800cb5ab7af3b98941c", "parents": [ "1a0163135df878114e520beab207abde36eb2502" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 19 13:59:27 2017 +0000" }, "committer": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Jan 19 14:41:52 2017 +0000" }, "message": "FDT.pm: add helper to get a node\u0027s full path\n\nThis will be useful for subsequent patches where we want to\nautomatically configure properties for nodes which may have arbitrary\nnames.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\n" } ], "next": "1a0163135df878114e520beab207abde36eb2502" }