tree 366e1c178de1216be0b4c34963bd363b7826cd7b
parent b6b446e659161e37bff1bc67de8ca26a30c24cb3
author Marc Zyngier <marc.zyngier@arm.com> 1403526306 +0100
committer Marc Zyngier <marc.zyngier@arm.com> 1439400514 +0100

irqchip: GIC: Convert to EOImode == 1

So far, GICv2 has been used in with EOImode == 0. The effect of this
mode is to perform the priority drop and the deactivation of the
interrupt at the same time.

While this works perfectly for Linux (we only have a single priority),
it causes issues when an interrupt is forwarded to a guest, and when
we want the guest to perform the EOI itself.

For this case, the GIC architecture provides EOImode == 1, where:
- A write to the EOI register drops the priority of the interrupt and leaves
it active. Other interrupts at the same priority level can now be taken,
but the active interrupt cannot be taken again
- A write to the DIR marks the interrupt as inactive, meaning it can
now be taken again.

We only enable this feature when booted in HYP mode and that
the device-tree reporte a suitable CPU interface. Observable behaviour
should remain unchanged.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>