| /include/ "skeleton.dtsi" |
| |
| / { |
| compatible = "nvidia,tegra30"; |
| interrupt-parent = <&intc>; |
| |
| aliases { |
| serial0 = &uarta; |
| serial1 = &uartb; |
| serial2 = &uartc; |
| serial3 = &uartd; |
| serial4 = &uarte; |
| }; |
| |
| host1x { |
| compatible = "nvidia,tegra30-host1x", "simple-bus"; |
| reg = <0x50000000 0x00024000>; |
| interrupts = <0 65 0x04 /* mpcore syncpt */ |
| 0 67 0x04>; /* mpcore general */ |
| clocks = <&tegra_car 28>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ranges = <0x54000000 0x54000000 0x04000000>; |
| |
| mpe { |
| compatible = "nvidia,tegra30-mpe"; |
| reg = <0x54040000 0x00040000>; |
| interrupts = <0 68 0x04>; |
| clocks = <&tegra_car 60>; |
| }; |
| |
| vi { |
| compatible = "nvidia,tegra30-vi"; |
| reg = <0x54080000 0x00040000>; |
| interrupts = <0 69 0x04>; |
| clocks = <&tegra_car 164>; |
| }; |
| |
| epp { |
| compatible = "nvidia,tegra30-epp"; |
| reg = <0x540c0000 0x00040000>; |
| interrupts = <0 70 0x04>; |
| clocks = <&tegra_car 19>; |
| }; |
| |
| isp { |
| compatible = "nvidia,tegra30-isp"; |
| reg = <0x54100000 0x00040000>; |
| interrupts = <0 71 0x04>; |
| clocks = <&tegra_car 23>; |
| }; |
| |
| gr2d { |
| compatible = "nvidia,tegra30-gr2d"; |
| reg = <0x54140000 0x00040000>; |
| interrupts = <0 72 0x04>; |
| clocks = <&tegra_car 21>; |
| }; |
| |
| gr3d { |
| compatible = "nvidia,tegra30-gr3d"; |
| reg = <0x54180000 0x00040000>; |
| clocks = <&tegra_car 24 &tegra_car 98>; |
| clock-names = "3d", "3d2"; |
| }; |
| |
| dc@54200000 { |
| compatible = "nvidia,tegra30-dc"; |
| reg = <0x54200000 0x00040000>; |
| interrupts = <0 73 0x04>; |
| clocks = <&tegra_car 27>, <&tegra_car 179>; |
| clock-names = "disp1", "parent"; |
| |
| rgb { |
| status = "disabled"; |
| }; |
| }; |
| |
| dc@54240000 { |
| compatible = "nvidia,tegra30-dc"; |
| reg = <0x54240000 0x00040000>; |
| interrupts = <0 74 0x04>; |
| clocks = <&tegra_car 26>, <&tegra_car 179>; |
| clock-names = "disp2", "parent"; |
| |
| rgb { |
| status = "disabled"; |
| }; |
| }; |
| |
| hdmi { |
| compatible = "nvidia,tegra30-hdmi"; |
| reg = <0x54280000 0x00040000>; |
| interrupts = <0 75 0x04>; |
| clocks = <&tegra_car 51>, <&tegra_car 189>; |
| clock-names = "hdmi", "parent"; |
| status = "disabled"; |
| }; |
| |
| tvo { |
| compatible = "nvidia,tegra30-tvo"; |
| reg = <0x542c0000 0x00040000>; |
| interrupts = <0 76 0x04>; |
| clocks = <&tegra_car 169>; |
| status = "disabled"; |
| }; |
| |
| dsi { |
| compatible = "nvidia,tegra30-dsi"; |
| reg = <0x54300000 0x00040000>; |
| clocks = <&tegra_car 48>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer@50004600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x50040600 0x20>; |
| interrupts = <1 13 0xf04>; |
| }; |
| |
| intc: interrupt-controller { |
| compatible = "arm,cortex-a9-gic"; |
| reg = <0x50041000 0x1000 |
| 0x50040100 0x0100>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| cache-controller { |
| compatible = "arm,pl310-cache"; |
| reg = <0x50043000 0x1000>; |
| arm,data-latency = <6 6 2>; |
| arm,tag-latency = <5 5 2>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| timer@60005000 { |
| compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| reg = <0x60005000 0x400>; |
| interrupts = <0 0 0x04 |
| 0 1 0x04 |
| 0 41 0x04 |
| 0 42 0x04 |
| 0 121 0x04 |
| 0 122 0x04>; |
| }; |
| |
| tegra_car: clock { |
| compatible = "nvidia,tegra30-car"; |
| reg = <0x60006000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| apbdma: dma { |
| compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| reg = <0x6000a000 0x1400>; |
| interrupts = <0 104 0x04 |
| 0 105 0x04 |
| 0 106 0x04 |
| 0 107 0x04 |
| 0 108 0x04 |
| 0 109 0x04 |
| 0 110 0x04 |
| 0 111 0x04 |
| 0 112 0x04 |
| 0 113 0x04 |
| 0 114 0x04 |
| 0 115 0x04 |
| 0 116 0x04 |
| 0 117 0x04 |
| 0 118 0x04 |
| 0 119 0x04 |
| 0 128 0x04 |
| 0 129 0x04 |
| 0 130 0x04 |
| 0 131 0x04 |
| 0 132 0x04 |
| 0 133 0x04 |
| 0 134 0x04 |
| 0 135 0x04 |
| 0 136 0x04 |
| 0 137 0x04 |
| 0 138 0x04 |
| 0 139 0x04 |
| 0 140 0x04 |
| 0 141 0x04 |
| 0 142 0x04 |
| 0 143 0x04>; |
| clocks = <&tegra_car 34>; |
| }; |
| |
| ahb: ahb { |
| compatible = "nvidia,tegra30-ahb"; |
| reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ |
| }; |
| |
| gpio: gpio { |
| compatible = "nvidia,tegra30-gpio"; |
| reg = <0x6000d000 0x1000>; |
| interrupts = <0 32 0x04 |
| 0 33 0x04 |
| 0 34 0x04 |
| 0 35 0x04 |
| 0 55 0x04 |
| 0 87 0x04 |
| 0 89 0x04 |
| 0 125 0x04>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| pinmux: pinmux { |
| compatible = "nvidia,tegra30-pinmux"; |
| reg = <0x70000868 0xd4 /* Pad control registers */ |
| 0x70003000 0x3e4>; /* Mux registers */ |
| }; |
| |
| /* |
| * There are two serial driver i.e. 8250 based simple serial |
| * driver and APB DMA based serial driver for higher baudrate |
| * and performace. To enable the 8250 based driver, the compatible |
| * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable |
| * the APB DMA based serial driver, the comptible is |
| * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". |
| */ |
| uarta: serial@70006000 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006000 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 36 0x04>; |
| nvidia,dma-request-selector = <&apbdma 8>; |
| clocks = <&tegra_car 6>; |
| status = "disabled"; |
| }; |
| |
| uartb: serial@70006040 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006040 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 37 0x04>; |
| nvidia,dma-request-selector = <&apbdma 9>; |
| clocks = <&tegra_car 160>; |
| status = "disabled"; |
| }; |
| |
| uartc: serial@70006200 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006200 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 46 0x04>; |
| nvidia,dma-request-selector = <&apbdma 10>; |
| clocks = <&tegra_car 55>; |
| status = "disabled"; |
| }; |
| |
| uartd: serial@70006300 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006300 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 90 0x04>; |
| nvidia,dma-request-selector = <&apbdma 19>; |
| clocks = <&tegra_car 65>; |
| status = "disabled"; |
| }; |
| |
| uarte: serial@70006400 { |
| compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006400 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 91 0x04>; |
| nvidia,dma-request-selector = <&apbdma 20>; |
| clocks = <&tegra_car 66>; |
| status = "disabled"; |
| }; |
| |
| pwm: pwm { |
| compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| reg = <0x7000a000 0x100>; |
| #pwm-cells = <2>; |
| clocks = <&tegra_car 17>; |
| }; |
| |
| rtc { |
| compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| reg = <0x7000e000 0x100>; |
| interrupts = <0 2 0x04>; |
| }; |
| |
| i2c@7000c000 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c000 0x100>; |
| interrupts = <0 38 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 12>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c400 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c400 0x100>; |
| interrupts = <0 84 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 54>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c500 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c500 0x100>; |
| interrupts = <0 92 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 67>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c700 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000c700 0x100>; |
| interrupts = <0 120 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 103>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000d000 { |
| compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| reg = <0x7000d000 0x100>; |
| interrupts = <0 53 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 47>, <&tegra_car 182>; |
| clock-names = "div-clk", "fast-clk"; |
| status = "disabled"; |
| }; |
| |
| spi@7000d400 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d400 0x200>; |
| interrupts = <0 59 0x04>; |
| nvidia,dma-request-selector = <&apbdma 15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 41>; |
| status = "disabled"; |
| }; |
| |
| spi@7000d600 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d600 0x200>; |
| interrupts = <0 82 0x04>; |
| nvidia,dma-request-selector = <&apbdma 16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 44>; |
| status = "disabled"; |
| }; |
| |
| spi@7000d800 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000d480 0x200>; |
| interrupts = <0 83 0x04>; |
| nvidia,dma-request-selector = <&apbdma 17>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 46>; |
| status = "disabled"; |
| }; |
| |
| spi@7000da00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000da00 0x200>; |
| interrupts = <0 93 0x04>; |
| nvidia,dma-request-selector = <&apbdma 18>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 68>; |
| status = "disabled"; |
| }; |
| |
| spi@7000dc00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000dc00 0x200>; |
| interrupts = <0 94 0x04>; |
| nvidia,dma-request-selector = <&apbdma 27>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 104>; |
| status = "disabled"; |
| }; |
| |
| spi@7000de00 { |
| compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| reg = <0x7000de00 0x200>; |
| interrupts = <0 79 0x04>; |
| nvidia,dma-request-selector = <&apbdma 28>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 105>; |
| status = "disabled"; |
| }; |
| |
| kbc { |
| compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| reg = <0x7000e200 0x100>; |
| interrupts = <0 85 0x04>; |
| clocks = <&tegra_car 36>; |
| status = "disabled"; |
| }; |
| |
| pmc { |
| compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; |
| reg = <0x7000e400 0x400>; |
| }; |
| |
| memory-controller { |
| compatible = "nvidia,tegra30-mc"; |
| reg = <0x7000f000 0x010 |
| 0x7000f03c 0x1b4 |
| 0x7000f200 0x028 |
| 0x7000f284 0x17c>; |
| interrupts = <0 77 0x04>; |
| }; |
| |
| iommu { |
| compatible = "nvidia,tegra30-smmu"; |
| reg = <0x7000f010 0x02c |
| 0x7000f1f0 0x010 |
| 0x7000f228 0x05c>; |
| nvidia,#asids = <4>; /* # of ASIDs */ |
| dma-window = <0 0x40000000>; /* IOVA start & length */ |
| nvidia,ahb = <&ahb>; |
| }; |
| |
| ahub { |
| compatible = "nvidia,tegra30-ahub"; |
| reg = <0x70080000 0x200 |
| 0x70080200 0x100>; |
| interrupts = <0 103 0x04>; |
| nvidia,dma-request-selector = <&apbdma 1>; |
| clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, |
| <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, |
| <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, |
| <&tegra_car 110>, <&tegra_car 162>; |
| clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| "spdif_in"; |
| ranges; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| tegra_i2s0: i2s@70080300 { |
| compatible = "nvidia,tegra30-i2s"; |
| reg = <0x70080300 0x100>; |
| nvidia,ahub-cif-ids = <4 4>; |
| clocks = <&tegra_car 30>; |
| status = "disabled"; |
| }; |
| |
| tegra_i2s1: i2s@70080400 { |
| compatible = "nvidia,tegra30-i2s"; |
| reg = <0x70080400 0x100>; |
| nvidia,ahub-cif-ids = <5 5>; |
| clocks = <&tegra_car 11>; |
| status = "disabled"; |
| }; |
| |
| tegra_i2s2: i2s@70080500 { |
| compatible = "nvidia,tegra30-i2s"; |
| reg = <0x70080500 0x100>; |
| nvidia,ahub-cif-ids = <6 6>; |
| clocks = <&tegra_car 18>; |
| status = "disabled"; |
| }; |
| |
| tegra_i2s3: i2s@70080600 { |
| compatible = "nvidia,tegra30-i2s"; |
| reg = <0x70080600 0x100>; |
| nvidia,ahub-cif-ids = <7 7>; |
| clocks = <&tegra_car 101>; |
| status = "disabled"; |
| }; |
| |
| tegra_i2s4: i2s@70080700 { |
| compatible = "nvidia,tegra30-i2s"; |
| reg = <0x70080700 0x100>; |
| nvidia,ahub-cif-ids = <8 8>; |
| clocks = <&tegra_car 102>; |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhci@78000000 { |
| compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| reg = <0x78000000 0x200>; |
| interrupts = <0 14 0x04>; |
| clocks = <&tegra_car 14>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000200 { |
| compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| reg = <0x78000200 0x200>; |
| interrupts = <0 15 0x04>; |
| clocks = <&tegra_car 9>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000400 { |
| compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| reg = <0x78000400 0x200>; |
| interrupts = <0 19 0x04>; |
| clocks = <&tegra_car 69>; |
| status = "disabled"; |
| }; |
| |
| sdhci@78000600 { |
| compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| reg = <0x78000600 0x200>; |
| interrupts = <0 31 0x04>; |
| clocks = <&tegra_car 15>; |
| status = "disabled"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <1>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <2>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <3>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupts = <0 144 0x04 |
| 0 145 0x04 |
| 0 146 0x04 |
| 0 147 0x04>; |
| }; |
| }; |
