PCI: apple: Configure link speeds properly
This sets the maximum link speed from the devicetree, and also requests
a link speed change from the controller. Without the request, the link
always comes up at Gen1 initially, and the core PCIe code complains
about a bandwidth bottleneck.
It turns out ASPM ends up retraining at a higher speed anyway even
without this code, but let's not rely on that.
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211122111332.72264-1-marcan@marcan.st
1 file changed
