WIP
Signed-off-by: Marc Zyngier <maz@kernel.org>
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 109a85e..5680f84 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -343,12 +343,11 @@
/*
* FGT register definitions
*
- * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
- * We're not using the generated masks as they are usually ahead of
- * the published ARM ARM, which we use as a reference.
+ * For each FGT register, define 3 constants:
*
- * Once we get to a point where the two describe the same thing, we'll
- * merge the definitions. One day.
+ * __H*FG*TR_EL2_RES0: the RES0 bits that apply to this register
+ * __H*FG*TR_EL2_MASK: the bits that are active when set to 1
+ * __H*FG*TR_EL2_nMASK: the bits that are RES0 or active when set to 0
*/
#define __HFGRTR_EL2_RES0 HFGxTR_EL2_RES0
#define __HFGRTR_EL2_MASK GENMASK(49, 0)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 092a73f..f92b224 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -84,7 +84,9 @@ enum cgt_group_id {
CGT_CPTR_TCPAC,
CGT_HCRX_EnFPM,
+ CGT_HCRX_SCTLR2En,
CGT_HCRX_TCR2En,
+ CGT_HCRX_TALLINT,
/*
* Anything after this point is a combination of coarse trap
@@ -379,12 +381,24 @@ static const struct trap_bits coarse_trap_bits[] = {
.mask = HCRX_EL2_EnFPM,
.behaviour = BEHAVE_FORWARD_ANY,
},
+ [CGT_HCRX_SCTLR2En] = {
+ .index = HCRX_EL2,
+ .value = 0,
+ .mask = HCRX_EL2_SCTLR2En,
+ .behaviour = BEHAVE_FORWARD_ANY,
+ },
[CGT_HCRX_TCR2En] = {
.index = HCRX_EL2,
.value = 0,
.mask = HCRX_EL2_TCR2En,
.behaviour = BEHAVE_FORWARD_ANY,
},
+ [CGT_HCRX_TALLINT] = {
+ .index = HCRX_EL2,
+ .value = 1,
+ .mask = HCRX_EL2_TALLINT,
+ .behaviour = BEHAVE_FORWARD_WRITE,
+ },
};
#define MCB(id, ...) \
