alx: improve self-test for FPGA
define new registers value for C0 version for register checking test,
and untouch PHY setting when do MAC loopback test.
PS. PHY external loopback isn't supported for FPGA due to board
limitation.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@do-not-panic.com>
diff --git a/src/alx_ethtool.c b/src/alx_ethtool.c
index 22e781c..02a8599 100644
--- a/src/alx_ethtool.c
+++ b/src/alx_ethtool.c
@@ -629,9 +629,103 @@
{0xffff, 0, 0, 0, 0, 0},
};
+struct alx_reg_attr ar816x_regs_c[] = {
+ {0x1400, 0xffff80E0, 0x4D00, 0x0, 0x40020000, 0},
+ {0x1404, 0x0, 0xffffffff, 0x0, 0x0, 1},
+ {0x1408, 0x0, 0xffffffff, 0x0, 0x0, 1},
+ {0x140c, 0xFFFF0000, 0x0, 0x0, 0xffff3800, 0},
+ {0x1410, 0xffffffff, 0x0, 0x0, 0x0000, 0},
+ {0x1414, 0x0, 0x0, 0x0, 0x0, 1},
+ {0x141C, 0xfffffffe, 0x0, 0x0, 0x0, 1},
+ {0x1420, 0xfffffffe, 0x0, 0x0, 0x0, 1},
+ {0x1484, 0x0, 0x7f7f7f7f, 0x0, 0x60405018, 1},
+ {0x1490, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1494, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1498, 0x0, 0xffff3ff, 0x0, 0x07a1f037, 1},
+ {0x149C, 0xffff0000, 0xffff, 0x0, 0x600, 1},
+ {0x14a0, 0x808078c0, 0x7f803f, 0x7f000700, 0x0, 1},
+ {0x14a4, 0x0, 0xFFFFFFFF, 0x0, 0x0, 1},
+ {0x14a8, 0xFF000000, 0x00FFFFFF, 0x0, 0x0, 1},
+ {0x1540, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1544, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1550, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1560, 0xFFFFF000, 0xfff, 0x0, 0x0, 0},
+ {0x1564, 0xFFFF0000, 0xffff, 0x0, 0x0, 0},
+ {0x1568, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1578, 0xFFFFF000, 0xfff, 0x0, 0x0, 0},
+ {0x157C, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1580, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1584, 0xFFFF0000, 0xffff, 0x0, 0x0, 0},
+ {0x1588, 0x0, 0xffffffff, 0x0, 0x0, 0},
+ {0x1590, 0xFF00, 0xFFFF00DF, 0x0, 0x01000045, 1},
+ {0x1594, 0xFFFFF800, 0x7FF, 0x0, 191, 1},
+ {0x15A0, 0x200E0040, 0x5FF1FFBF, 0x0, 0x40810083, 1},
+ {0x15A4, 0xFFFFF000, 0xFFF, 0x0, 0x1210, 1},
+ {0x15A8, 0xF000F000, 0x0FFF0FFF, 0x0, 0x02E009C0, 1},
+ {0x15AC, 0xF000, 0xFFFF0FFF, 0x0, 0x0100, 1},
+ {0x15C4, 0xFF000000, 0xFFFFFF, 0x0, 0x0, 1},
+ {0x15C8, 0xFFFF0000, 0xFFFF, 0x0, 0x0100, 1},
+ {0x15E0, 0xFFFFF000, 0xFFF, 0x0, 0x0, 1},
+ {0x15F0, 0x0, 0xFFFFFFFF, 0x0, 0x0, 1},
+ {0x15F4, 0xFFFFFFFF, 0x0, 0x0, 0x0, 1},
+ {0x15F8, 0xFFFFFFFF, 0x0, 0x0, 0x0, 1},
+ {0x15FC, 0xFFFFFFFF, 0x0, 0x0, 0x0, 1},
+ {0x1700, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1704, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1708, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x170c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1710, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1714, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1718, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x171c, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x1720, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x1724, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x1728, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x172c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1730, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1734, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1738, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x173c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1740, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1744, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1748, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x174c, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x1750, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1754, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x1758, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x175c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1760, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1764, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1768, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x176c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1770, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x1774, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1778, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x177c, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x1780, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1784, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1788, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x178c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1790, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1794, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x1798, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x179c, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x17a0, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x17a4, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x17a8, 0xffffffff, 0x0, 0xffffff, 0x0, 1},
+ {0x17ac, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x17b0, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x17b4, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x17b8, 0xffffffff, 0x0, 0xffff, 0x0, 1},
+ {0x17bc, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0x17c0, 0xffffffff, 0x0, 0xffffffff, 0x0, 1},
+ {0xffff, 0, 0, 0, 0, 0},
+};
+
static int alx_diag_register(struct alx_adapter *adpt, u64 *data)
{
struct alx_hw *hw = &adpt->hw;
+ u8 rev = ALX_REVID(hw);
struct alx_reg_attr *preg, *oreg;
u32 val, old;
@@ -640,8 +734,12 @@
case ALX_DEV_ID_AR8162:
case ALX_DEV_ID_AR8171:
case ALX_DEV_ID_AR8172:
- oreg = ALX_REV_B0 == ALX_REVID(hw) ?
- ar816x_regs_b : ar816x_regs_a;
+ if (rev == ALX_REV_B0)
+ oreg = ar816x_regs_b;
+ else if (rev == ALX_REV_C0)
+ oreg = ar816x_regs_c;
+ else
+ oreg = ar816x_regs_a;
break;
default:
/* unknow type */
@@ -1463,6 +1561,13 @@
ALX_MAC_CTRL_DBG_EN;
/* PHY configuration */
+ if (hw->is_fpga) {
+ if (mode == ALX_LPBK_MAC)
+ goto cfg_hw;
+ netif_err(adpt, hw, adpt->netdev,
+ "loopback: FPGA not support PHY external lpbk!\n");
+ goto err_hw;
+ }
err = alx_write_phy_reg(hw, 16, 0x0800);
if (err) {
netif_err(adpt, hw, adpt->netdev,
@@ -1504,6 +1609,7 @@
hw->rx_ctrl &= ~ALX_MAC_CTRL_LPBACK_EN;
}
+cfg_hw:
alx_init_intr(adpt);
alx_init_def_rss_idt(adpt);
err = alx_setup_all_ring_resources(adpt);
@@ -1532,6 +1638,8 @@
struct alx_hw *hw = &adpt->hw;
u32 val;
+ hw->link_up = false;
+ hw->link_speed = SPEED_0;
alx_reset_mac(hw);
hw->rx_ctrl &= ~(ALX_MAC_CTRL_LPBACK_EN | ALX_MAC_CTRL_DBG_EN);
alx_enable_aspm(hw, false, false);
@@ -1544,8 +1652,12 @@
static int alx_diag_loopback(struct alx_adapter *adpt, u64 *data, bool phy_lpbk)
{
+ struct alx_hw *hw = &adpt->hw;
int i, err;
+ if (hw->is_fpga && phy_lpbk)
+ return 0;
+
for (i = 0; i < ARRAY_SIZE(alx_diag_speed); i++) {
err = alx_diag_lpbk_init_hw(
adpt,
diff --git a/src/alx_hw.c b/src/alx_hw.c
index 5922a65..b9a2a3f 100644
--- a/src/alx_hw.c
+++ b/src/alx_hw.c
@@ -157,7 +157,7 @@
* PERST, driver need re-calibrate before enter Sleep for WoL
*/
ALX_MEM_R32(hw, ALX_MISC, &val);
- if (rev == ALX_REV_B0) {
+ if (rev >= ALX_REV_B0) {
/* restore over current protection def-val,
* this val could be reset by MAC-RST
*/
@@ -270,6 +270,11 @@
ALX_MEM_W32(hw, ALX_SERDES,
val | ALX_SERDES_MACCLK_SLWDWN | ALX_SERDES_PHYCLK_SLWDWN);
+ /* mac reset cause MDIO ctrl restore non-polling status */
+ if (hw->is_fpga)
+ __alx_start_phy_polling(hw, ALX_MDIO_CLK_SEL_25MD128);
+
+
return ret;
}
@@ -1209,7 +1214,7 @@
ALX_MEM_W32(hw, ALX_CLK_GATE, ALX_CLK_GATE_ALL_A0);
/* idle timeout to switch clk_125M */
- if (chip_rev == ALX_REV_B0) {
+ if (chip_rev >= ALX_REV_B0) {
ALX_MEM_W32(hw, ALX_IDLE_DECISN_TIMER,
ALX_IDLE_DECISN_TIMER_DEF);
}
diff --git a/src/alx_hw.h b/src/alx_hw.h
index 2f0dcb8..257a58c 100644
--- a/src/alx_hw.h
+++ b/src/alx_hw.h
@@ -630,6 +630,7 @@
void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
int alx_select_powersaving_speed(struct alx_hw *hw, u16 *speed);
void __alx_update_hw_stats(struct alx_hw *hw);
+void __alx_start_phy_polling(struct alx_hw *hw, u16 clk_sel);
#define alx_get_readrq(_hw) pcie_get_readrq((_hw)->pdev)
#define alx_set_readrq(_hw, _v) pcie_set_readrq((_hw)->pdev, _v)
