| commit | 73ba85937b2a07b6401ba0b7ca06a112762de9f7 | [log] [tgz] |
|---|---|---|
| author | Borislav Petkov <borislav.petkov@amd.com> | Mon Sep 19 17:34:45 2011 +0200 |
| committer | Borislav Petkov <borislav.petkov@amd.com> | Thu Oct 06 12:34:05 2011 +0200 |
| tree | f4905768cf9cc469b79e92a3c7cf9dec2c6079b1 | |
| parent | b0b07a2bd4fbb6198d4e7142337214eeb77c417a [diff] |
amd64_edac: Add a fix for Erratum 505 When accessing the scrub rate control register (F3x58) on F15h, the DRAM controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the scrub rate configuration can take effect. See Erratum 505 in the AMD F15h revision guide for more details. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>